/* * dma_helper.c * * Created on: Sep 18, 2019 * Author: abody */ #include #ifndef MOCKABLE #define MOCKABLE(x) x #endif namespace f4ll_cpp { DmaHelper::DmaHelper(DMA_TypeDef *dma, uint32_t stream) { m_dma = dma; m_stream = stream; m_isReg = _GetIsReg(dma, stream); m_ifcReg = _GetIfcReg(dma, stream); m_feMask = _GetFeMask(stream); m_dmeMask = _GetDmeMask(stream); m_teMask = _GetTeMask(stream); m_htMask = _GetHtMask(stream); m_tcMask = _GetTcMask(stream); } volatile uint32_t* DmaHelper::_GetIsReg(DMA_TypeDef *dma, uint32_t stream) { if(dma == DMA1) return (stream < LL_DMA_STREAM_4) ? &DMA1->LISR : &DMA1->HISR; else return (stream < LL_DMA_STREAM_4) ? &DMA2->LISR : &DMA2->HISR; } volatile uint32_t* DmaHelper::_GetIfcReg(DMA_TypeDef *dma, uint32_t stream) { if(dma == DMA1) return (stream < LL_DMA_STREAM_4) ? &DMA1->LIFCR : &DMA1->HIFCR; else return (stream < LL_DMA_STREAM_4) ? &DMA2->LIFCR : &DMA2->HIFCR; } uint32_t DmaHelper::_GetFeMask(uint32_t stream) { static const uint32_t feMasks[8] = { DMA_LISR_FEIF0, DMA_LISR_FEIF1, DMA_LISR_FEIF2, DMA_LISR_FEIF3, DMA_HISR_FEIF4, DMA_HISR_FEIF5, DMA_HISR_FEIF6, DMA_HISR_FEIF7 }; return feMasks[stream]; } uint32_t DmaHelper::_GetDmeMask(uint32_t stream) { static const uint32_t dmeMasks[8] = { DMA_LISR_DMEIF0, DMA_LISR_DMEIF1, DMA_LISR_DMEIF2, DMA_LISR_DMEIF3, DMA_HISR_DMEIF4, DMA_HISR_DMEIF5, DMA_HISR_DMEIF6, DMA_HISR_DMEIF7 }; return dmeMasks[stream]; } uint32_t DmaHelper::_GetTeMask(uint32_t stream) { static const uint32_t teMasks[8] = { DMA_LISR_TEIF0, DMA_LISR_TEIF1, DMA_LISR_TEIF2, DMA_LISR_TEIF3, DMA_HISR_TEIF4, DMA_HISR_TEIF5, DMA_HISR_TEIF6, DMA_HISR_TEIF7 }; return teMasks[stream]; } uint32_t DmaHelper::_GetHtMask(uint32_t stream) { static const uint32_t htMasks[8] = { DMA_LISR_HTIF0, DMA_LISR_HTIF1, DMA_LISR_HTIF2, DMA_LISR_HTIF3, DMA_HISR_HTIF4, DMA_HISR_HTIF5, DMA_HISR_HTIF6, DMA_HISR_HTIF7 }; return htMasks[stream]; } uint32_t DmaHelper::_GetTcMask(uint32_t stream) { static const uint32_t tcMasks[8] = { DMA_LISR_TCIF0, DMA_LISR_TCIF1, DMA_LISR_TCIF2, DMA_LISR_TCIF3, DMA_HISR_TCIF4, DMA_HISR_TCIF5, DMA_HISR_TCIF6, DMA_HISR_TCIF7 }; return tcMasks[stream]; } } // f4ll_cpp