STM32CubeIDE and package upgrade
This commit is contained in:
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5139921a22
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ecdfc9003a
89 changed files with 2838 additions and 2207 deletions
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@ -7,13 +7,12 @@
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2019 STMicroelectronics.
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* All rights reserved.</center></h2>
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* Copyright (c) 2021 STMicroelectronics.
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* All rights reserved.
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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@ -38,14 +37,16 @@ extern "C" {
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#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
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#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
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#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
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#if defined(STM32U5)
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#if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1)
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#define CRYP_DATATYPE_32B CRYP_NO_SWAP
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#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP
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#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP
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#define CRYP_DATATYPE_1B CRYP_BIT_SWAP
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#if defined(STM32U5)
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#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF
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#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF
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#endif /* STM32U5 */
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#endif /* STM32U5 || STM32H7 || STM32MP1 */
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/**
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* @}
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*/
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@ -105,6 +106,13 @@ extern "C" {
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#if defined(STM32H7)
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#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT
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#endif /* STM32H7 */
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#if defined(STM32U5)
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#define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES
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#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES
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#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5
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#endif /* STM32U5 */
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/**
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* @}
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*/
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@ -214,10 +222,23 @@ extern "C" {
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* @{
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*/
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#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
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#if defined(STM32U5)
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#define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE
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#define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE
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#define MPU_DEVICE_nGRE MPU_DEVICE_NGRE
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#endif /* STM32U5 */
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/**
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* @}
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*/
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/** @defgroup CRC_Aliases CRC API aliases
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* @{
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*/
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#if defined(STM32C0)
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#else
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#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
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#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
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#endif
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/**
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* @}
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*/
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@ -252,6 +273,13 @@ extern "C" {
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#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
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#endif
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#if defined(STM32U5)
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#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1
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#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1
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#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1
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#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1
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#endif
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#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
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#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
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#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
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@ -394,6 +422,10 @@ extern "C" {
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#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
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#endif /* STM32H7 */
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#if defined(STM32U5)
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#define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI
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#endif /* STM32U5 */
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/**
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* @}
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*/
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@ -473,7 +505,7 @@ extern "C" {
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#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
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#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
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#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
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#if defined(STM32G0)
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#if defined(STM32G0) || defined(STM32C0)
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#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE
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#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH
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#else
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@ -637,6 +669,24 @@ extern "C" {
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#endif /* STM32F0 || STM32F3 || STM32F1 */
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#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
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#if defined(STM32U5)
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#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ
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#endif /* STM32U5 */
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#if defined(STM32U5)
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#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP
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#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1
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#endif /* STM32U5 */
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/**
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* @}
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*/
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/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose
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* @{
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*/
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#if defined(STM32U5)
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#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI
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#endif /* STM32U5 */
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/**
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* @}
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*/
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@ -874,9 +924,19 @@ extern "C" {
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#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
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#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
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/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
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* @{
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*/
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#define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue
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/**
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* @}
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*/
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#if defined(STM32U5)
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#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF
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#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF
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#define LPTIM_CHANNEL_ALL 0x00000000U
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#endif /* STM32U5 */
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/**
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* @}
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@ -1029,8 +1089,8 @@ extern "C" {
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#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
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#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
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#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
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#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
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#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
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#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
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#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
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#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
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@ -1041,15 +1101,22 @@ extern "C" {
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#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
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#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
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#if defined(STM32F7)
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#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
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#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK
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#endif /* STM32F7 */
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#if defined(STM32H7)
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#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
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#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
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#endif /* STM32H7 */
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#if defined(STM32F7) || defined(STM32H7)
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#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
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#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
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#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
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#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL
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#endif /* STM32H7 */
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#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP
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#endif /* STM32F7 || STM32H7 */
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/**
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* @}
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#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
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#endif
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#if defined(STM32U5) || defined(STM32MP2)
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#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS
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#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK
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#endif
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/**
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* @}
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*/
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#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
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#if defined (STM32U5)
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#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP
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#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP
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#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP
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#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP
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#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP
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#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP
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#define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP
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#define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP
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#define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP
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#define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP
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#define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP
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#define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP
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#define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP
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#define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP
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#define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP
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#define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP
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#define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP
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#define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP
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#define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP
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#define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP
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#define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP
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#define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP
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#define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP
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#define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP
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#define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP
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#define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP
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#define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP
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#define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP
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#define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP
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#define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP
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#define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP
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#define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP
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#define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP
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#define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP
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#define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP
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#define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP
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#define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP
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#define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP
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#define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP
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#define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP
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#define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP
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#define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP
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#define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP
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#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP
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#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP
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#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP
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#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP
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#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP
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#define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP
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#define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP
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#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP
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#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP
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#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP
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#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY
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#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY
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#define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY
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#define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN
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#define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN
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#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN
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#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN
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#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN
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#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK
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#endif
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/**
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* @}
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*/
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#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
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#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
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#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
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#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) || defined(STM32C0)
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#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
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#else
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#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
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#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
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#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
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#if defined(STM32U5)
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#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL
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#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL
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#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL
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#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL
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#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE
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#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE
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#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE
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#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE
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#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE
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#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT
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#endif
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#define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK
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#define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48
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#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2
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#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1
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#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK
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#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
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#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
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#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
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#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
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#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
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#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
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#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE
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#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE
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#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE
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#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE
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#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE
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#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG
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#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE
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#endif /* STM32U5 */
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|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -3421,7 +3584,9 @@ extern "C" {
|
|||
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5)
|
||||
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx)|| \
|
||||
defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
|
||||
defined (STM32C0)
|
||||
#else
|
||||
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
|
||||
#endif
|
||||
|
|
@ -3485,7 +3650,7 @@ extern "C" {
|
|||
#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
|
||||
#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
|
||||
|
||||
#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32L1)
|
||||
#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1)
|
||||
#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE
|
||||
#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE
|
||||
#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE
|
||||
|
|
@ -3822,6 +3987,16 @@ extern "C" {
|
|||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#if defined (STM32F7)
|
||||
#define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE
|
||||
#endif /* STM32F7 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -3836,5 +4011,4 @@ extern "C" {
|
|||
|
||||
#endif /* STM32_HAL_LEGACY */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue