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STM32CubeIDE and package upgrade

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This commit is contained in:
Attila Body 2022-09-05 16:00:02 +02:00
parent 5139921a22
commit ecdfc9003a
89 changed files with 2838 additions and 2207 deletions
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77
Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h
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@ -12,13 +12,12 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@ -13247,7 +13246,7 @@ typedef struct
/* Ethernet MMC Registers bits definition */
/******************************************************************************/
/* Bit definition for Ethernet MMC Contol Register */
/* Bit definition for Ethernet MMC Control Register */
#define ETH_MMCCR_MCFHP_Pos (5U)
#define ETH_MMCCR_MCFHP_Msk (0x1UL << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */
#define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
@ -13331,7 +13330,7 @@ typedef struct
#define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */
#define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
/* Bit definition for Ethernet MMC Received Frames with Alignment Error Counter Register */
#define ETH_MMCRFAECR_RFAEC_Pos (0U)
#define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */
#define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
@ -13345,34 +13344,37 @@ typedef struct
/* Ethernet PTP Registers bits definition */
/******************************************************************************/
/* Bit definition for Ethernet PTP Time Stamp Contol Register */
/* Bit definition for Ethernet PTP Time Stamp Control Register */
#define ETH_PTPTSCR_TSPFFMAE_Pos (18U)
#define ETH_PTPTSCR_TSPFFMAE_Msk (0x1UL << ETH_PTPTSCR_TSPFFMAE_Pos) /*!< 0x00008000 */
#define ETH_PTPTSCR_TSPFFMAE ETH_PTPTSCR_TSPFFMAE_Msk /* Time stamp PTP frame filtering MAC address enable */
#define ETH_PTPTSCR_TSCNT_Pos (16U)
#define ETH_PTPTSCR_TSCNT_Msk (0x3UL << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */
#define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
#define ETH_PTPTSSR_TSSMRME_Pos (15U)
#define ETH_PTPTSSR_TSSMRME_Msk (0x1UL << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */
#define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
#define ETH_PTPTSSR_TSSEME_Pos (14U)
#define ETH_PTPTSSR_TSSEME_Msk (0x1UL << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */
#define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */
#define ETH_PTPTSSR_TSSIPV4FE_Pos (13U)
#define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */
#define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
#define ETH_PTPTSSR_TSSIPV6FE_Pos (12U)
#define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */
#define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
#define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U)
#define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
#define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
#define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U)
#define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
#define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
#define ETH_PTPTSSR_TSSSR_Pos (9U)
#define ETH_PTPTSSR_TSSSR_Msk (0x1UL << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */
#define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
#define ETH_PTPTSSR_TSSARFE_Pos (8U)
#define ETH_PTPTSSR_TSSARFE_Msk (0x1UL << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */
#define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
#define ETH_PTPTSCR_TSSMRME_Pos (15U)
#define ETH_PTPTSCR_TSSMRME_Msk (0x1UL << ETH_PTPTSCR_TSSMRME_Pos) /*!< 0x00008000 */
#define ETH_PTPTSCR_TSSMRME ETH_PTPTSCR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
#define ETH_PTPTSCR_TSSEME_Pos (14U)
#define ETH_PTPTSCR_TSSEME_Msk (0x1UL << ETH_PTPTSCR_TSSEME_Pos) /*!< 0x00004000 */
#define ETH_PTPTSCR_TSSEME ETH_PTPTSCR_TSSEME_Msk /* Time stamp snapshot for event message enable */
#define ETH_PTPTSCR_TSSIPV4FE_Pos (13U)
#define ETH_PTPTSCR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV4FE_Pos) /*!< 0x00002000 */
#define ETH_PTPTSCR_TSSIPV4FE ETH_PTPTSCR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
#define ETH_PTPTSCR_TSSIPV6FE_Pos (12U)
#define ETH_PTPTSCR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV6FE_Pos) /*!< 0x00001000 */
#define ETH_PTPTSCR_TSSIPV6FE ETH_PTPTSCR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
#define ETH_PTPTSCR_TSSPTPOEFE_Pos (11U)
#define ETH_PTPTSCR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSCR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
#define ETH_PTPTSCR_TSSPTPOEFE ETH_PTPTSCR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
#define ETH_PTPTSCR_TSPTPPSV2E_Pos (10U)
#define ETH_PTPTSCR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSCR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
#define ETH_PTPTSCR_TSPTPPSV2E ETH_PTPTSCR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
#define ETH_PTPTSCR_TSSSR_Pos (9U)
#define ETH_PTPTSCR_TSSSR_Msk (0x1UL << ETH_PTPTSCR_TSSSR_Pos) /*!< 0x00000200 */
#define ETH_PTPTSCR_TSSSR ETH_PTPTSCR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
#define ETH_PTPTSCR_TSSARFE_Pos (8U)
#define ETH_PTPTSCR_TSSARFE_Msk (0x1UL << ETH_PTPTSCR_TSSARFE_Pos) /*!< 0x00000100 */
#define ETH_PTPTSCR_TSSARFE ETH_PTPTSCR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
#define ETH_PTPTSCR_TSARU_Pos (5U)
#define ETH_PTPTSCR_TSARU_Msk (0x1UL << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */
@ -13452,6 +13454,9 @@ typedef struct
/******************************************************************************/
/* Bit definition for Ethernet DMA Bus Mode Register */
#define ETH_DMABMR_MB_Pos (26U)
#define ETH_DMABMR_MB_Msk (0x1UL << ETH_DMABMR_MB_Pos) /*!< 0x04000000 */
#define ETH_DMABMR_MB ETH_DMABMR_MB_Msk /* Mixed Burst */
#define ETH_DMABMR_AAB_Pos (25U)
#define ETH_DMABMR_AAB_Msk (0x1UL << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */
#define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
@ -15295,7 +15300,7 @@ typedef struct
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
((INSTANCE) == TIM5))
/***************** TIM Instances : external trigger input availabe ************/
/***************** TIM Instances : external trigger input available ************/
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
@ -15600,7 +15605,3 @@ typedef struct
#endif /* __cplusplus */
#endif /* __STM32F407xx_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/