Kinda works
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286
components/f4ll_cpp/packetuart.cpp
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286
components/f4ll_cpp/packetuart.cpp
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/*
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* usart_handler.c
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*
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* Created on: Sep 16, 2019
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* Author: abody
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*/
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#include <f4ll_cpp/memcpydma.h>
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#include "f4ll_cpp/crcscheduler.h"
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#include <f4ll_cpp/packetuart.h>
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#include <string.h>
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#include <platform/usart_ll.h>
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#if defined(HAVE_DIAG)
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#include "diag.h"
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#endif
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#ifndef MOCKABLE
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#define MOCKABLE(x) x
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#endif
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#ifndef DIAG_RX_BUFFER_SWITCH
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# define DIAG_RX_BUFFER_SWITCH(x)
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#endif
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#ifndef DIAG_INTERRUPT_IN
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# define DIAG_INTERRUPT_IN()
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#endif
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#ifndef DIAG_INTERRUPT_OUT
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# define DIAG_INTERRUPT_OUT()
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#endif
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#define STARTMARKER 0x95
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namespace f4ll_cpp
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{
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static inline uint32_t RoundUpTo4(uint32_t inp)
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{
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return (inp + 3) & 0xfffc;
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}
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#ifndef USART_STATS_DISABLED
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static inline void StatsIncOverrun(struct usart_stats *s) {
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++s->overrun;
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}
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static inline void StatsIncHdrError(struct usart_stats *s, uint32_t hdr) {
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++s->hdrError;
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s->lastErrHdr = hdr;
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}
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static inline void StatsIncPayloadError(struct usart_stats *s, uint32_t pep1, uint32_t pep2) {
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++s->payloadErrror;
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s->pep1 = pep1;
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s->pep2 = pep2;
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}
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static inline void StatsIncDmaError(struct usart_stats *s) {
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++s->dmaError;
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}
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static inline void StatsIncRcvd(struct usart_stats *s) {
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++s->rcvd;
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}
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static inline void StatsIncPremature_hdr(struct usart_stats *s) {
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++s->premature_hdr;
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}
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static inline void StatsIncPremature_payload(struct usart_stats *s) {
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++s->premature_payload;
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}
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static inline void StatsIncSent(struct usart_stats *s) {
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++s->sent;
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}
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static inline void StatsAddSkiped(struct usart_stats *s, uint8_t cnt) {
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s->skiped += s->rcvd > 2 ? cnt : 0;
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}
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#else // USART_STATS_DISABLED
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#define StatsIncOverrun(x)
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#define StatsIncHdrError(x,y)
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#define StatsIncPayloadError(x,y,z)
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#define StatsIncDmaError(x)
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#define StatsIncRcvd(x)
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#define StatsIncPremature_hdr(x)
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#define StatsIncPremature_payload(x)
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#define StatsIncSent(x)
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#define StatsAddSkiped(x,y)
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#endif // USART_STATS_DISABLED
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PacketUart::PacketUart(
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USART_TypeDef *uart, DMA_TypeDef *dma, uint32_t stream_rx, uint32_t stream_tx, CrcScheduler *crcScheduler,
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PacketUart::pku_packetreceivedcallback_t packetReceivedCallback, void * packetReceivedCallbackParam)
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: UartBase(uart, dma, stream_rx, stream_tx)
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, m_crcScheduler(crcScheduler)
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{
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uint32_t status = uart->SR;
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volatile uint32_t tmpreg = uart->DR; // clearing some of the error/status bits in the USART
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(void) tmpreg;
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(void) status;
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txBuffer.busy = 0;
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txBuffer.error = 0;
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txBuffer.requestedLength = 0;
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rxBuffers[0].busy = 0;
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rxBuffers[1].busy = 0;
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rxBuffers[0].error = 0;
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rxBuffers[1].error = 0;
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rxBuffers[0].requestedLength = 0;
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rxBuffers[1].requestedLength = 0;
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packetReceivedCallback = packetReceivedCallback;
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packetReceivedCallbackParam = packetReceivedCallbackParam;
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rxSerial = -1;
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txSerial = 0;
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activeRxBuf = 0;
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m_crcScheduler->AttachTasks( &crcSlot, crcTasks, 2);
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#ifndef USART_STATS_DISABLED
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memset(&st->stats, 0, sizeof(st->stats));
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#endif
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LL_USART_EnableIT_IDLE(uart);
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}
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uint8_t* PacketUart::GetTxBuffer()
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{
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return txBuffer.packet.payload;
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}
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uint8_t PacketUart::CheckHeader(Packet *packet)
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{
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return packet->header.startByte == STARTMARKER && (packet->header.startByte ^ packet->header.serial ^ packet->header.payloadLength) == packet->header.hash;
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}
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uint8_t PacketUart::Post(uint8_t const *payload, uint8_t length, uint8_t waitForCrcQueue)
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{
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struct Buffer *buffer = &txBuffer;
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uint8_t hash = STARTMARKER;
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buffer->packet.header.startByte = STARTMARKER;
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buffer->packet.header.serial = txSerial;
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hash ^= txSerial++;
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buffer->packet.header.payloadLength = length;
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hash ^= length;
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buffer->packet.header.hash = hash;
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uint16_t payloadLength = RoundUpTo4(length);
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if(payload)
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memcpy(txBuffer.packet.payload, payload, length);
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txBuffer.requestedLength = sizeof(struct Header) + payloadLength + sizeof(uint32_t); // +4 for the hash
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txBuffer.busy = 1;
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txBuffer.error = 0;
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m_crcScheduler->Enqueue(&crcSlot, 0, &txBuffer.packet, sizeof(txBuffer.packet.header) + payloadLength,
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NULL, (uint32_t*)(txBuffer.packet.payload + payloadLength));
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while(waitForCrcQueue && m_crcScheduler->IsTaskQueued(&crcSlot, 0));
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SetupTransmit(&txBuffer.packet, txBuffer.requestedLength);
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StatsIncSent(&status->stats);
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return 0;
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}
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void PacketUart::SetupReceive()
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{
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uint8_t packetIndex = activeRxBuf;
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rxBuffers[packetIndex].requestedLength = sizeof(rxBuffers[packetIndex].packet);
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UartBase::SetupReceive(&rxBuffers[packetIndex], sizeof(rxBuffers[packetIndex].packet));
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}
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void PacketUart::ConsumePacket(uint8_t packetIndex)
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{
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Buffer *buffer = &rxBuffers[packetIndex];
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if(buffer->busy) {
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if(buffer->error)
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StatsIncPayloadError(&status->stats, Buffer->errorInfo, *(uint32_t*) (Buffer->packet.payload + RoundUpTo4(Buffer->packet.header.payloadLength)));
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else {
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uint8_t diff = buffer->packet.header.serial - rxSerial;
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if(diff > 1)
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StatsAddSkiped(&status->stats, diff - 1);
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rxSerial = buffer->packet.header.serial;
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}
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}
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buffer->busy = buffer->error = 0;
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}
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void PacketUart::HandleRxDmaIrq()
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{
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DIAG_INTERRUPT_IN();
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StatsIncRcvd(&status->stats);
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if(*m_rxDma.GetIsReg() & m_rxDma.GetTcMask()) {
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*m_rxDma.GetIfcReg() = m_rxDma.GetTcMask();
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if(CheckHeader(&rxBuffers[activeRxBuf].packet)) {
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m_crcScheduler->Enqueue(&crcSlot, 1, &rxBuffers[activeRxBuf].packet,
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RoundUpTo4(rxBuffers[activeRxBuf].packet.header.payloadLength) + sizeof(struct Header),
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this, &rxBuffers[activeRxBuf]);
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} else {
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StatsIncHdrError(&status->stats, *(uint32_t*)&status->rxBuffers[status->activeRxBuf].packet.header);
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rxBuffers[activeRxBuf].error = 1;
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}
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}
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if(*m_rxDma.GetIsReg() & m_rxDma.GetTeMask()) {
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*m_rxDma.GetIfcReg() = m_rxDma.GetTeMask();
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rxBuffers[activeRxBuf].error = 1;
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}
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activeRxBuf ^= 1;
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DIAG_RX_BUFFER_SWITCH(status->activeRxBuf);
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if(rxBuffers[activeRxBuf].busy)
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StatsIncOverrun(&status->stats);
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SetupReceive();
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DIAG_INTERRUPT_OUT();
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}
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void PacketUart::CrcCalculationCompleted(void *callbackParm, uint32_t calculatedCrc, uint8_t success)
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{
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struct Buffer *ub = (struct Buffer*) callbackParm;
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if(!success)
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ub->error = 1;
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else if(*(uint32_t*) (ub->packet.payload + RoundUpTo4(ub->packet.header.payloadLength)) == calculatedCrc)
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ub->busy = 1;
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else {
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ub->error = ub->busy = 1;
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ub->errorInfo = calculatedCrc;
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}
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if(packetReceivedCallback)
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packetReceivedCallback(packetReceivedCallbackParam, ub);
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}
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void PacketUart::HandleTxDmaIrq()
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{
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DIAG_INTERRUPT_IN();
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if(*m_txDma.GetIsReg() & m_txDma.GetTcMask()) { // DMA transfer complete
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*m_txDma.GetIfcReg() = m_txDma.GetTcMask();
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LL_USART_EnableIT_TC(m_uart);
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LL_DMA_DisableStream(m_txDma.GetDma(), m_txDma.GetStream());
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}
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if(*m_txDma.GetIsReg() & m_txDma.GetTeMask()) {
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*m_txDma.GetIfcReg() = m_txDma.GetTeMask();
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txBuffer.error = 1;
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LL_USART_EnableIT_TC(m_uart);
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LL_DMA_DisableStream(m_txDma.GetDma(), m_txDma.GetStream());
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StatsIncDmaError(&status->stats);
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}
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if(*m_txDma.GetIsReg() & m_txDma.GetFeMask())
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*m_txDma.GetIfcReg() = m_txDma.GetFeMask();
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if(*m_txDma.GetIsReg() & m_txDma.GetHtMask())
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*m_txDma.GetIfcReg() = m_txDma.GetHtMask();
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if(*m_txDma.GetIsReg() & m_txDma.GetDmeMask())
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*m_txDma.GetIfcReg() = m_txDma.GetDmeMask();
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DIAG_INTERRUPT_OUT();
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}
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void PacketUart::HandleUsartIrq()
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{
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DIAG_INTERRUPT_IN();
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if(LL_USART_IsActiveFlag_IDLE(m_uart) && LL_USART_IsEnabledIT_IDLE(m_uart)) { // receiver idle
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LL_USART_ClearFlag_IDLE(m_uart);
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uint16_t rcvdLen = rxBuffers[activeRxBuf].requestedLength - LL_DMA_GetDataLength(m_rxDma.GetDma(), m_rxDma.GetStream());
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if(rcvdLen >= sizeof(struct Header)) {
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if(CheckHeader(&rxBuffers[activeRxBuf].packet)) {
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if(rcvdLen >= sizeof(struct Header) + RoundUpTo4(rxBuffers[activeRxBuf].packet.header.payloadLength) + sizeof(uint32_t))
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LL_DMA_DisableStream(m_rxDma.GetDma(), m_rxDma.GetStream());
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else
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StatsIncPremature_payload(&stats);
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} else {
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rxBuffers[activeRxBuf].error = 1;
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rxBuffers[activeRxBuf].busy = 1;
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LL_DMA_DisableStream(m_rxDma.GetDma(), m_rxDma.GetStream());
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}
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} else
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StatsIncPremature_hdr(&status->stats);
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}
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if(LL_USART_IsActiveFlag_TC(m_uart) && LL_USART_IsEnabledIT_TC(m_uart)) { // transmission complete
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LL_USART_DisableIT_TC(m_uart);
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LL_USART_DisableDirectionTx(m_uart); // enforcing an idle frame
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LL_USART_EnableDirectionTx(m_uart);
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txBuffer.busy = 0;
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}
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DIAG_INTERRUPT_OUT();
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}
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} // f4ll_cpp
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