F417 -> F407 oooops
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98aacc5c47
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7 changed files with 171 additions and 489 deletions
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@ -1,8 +1,8 @@
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/**
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******************************************************************************
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* @file stm32f417xx.h
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* @file stm32f407xx.h
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* @author MCD Application Team
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* @brief CMSIS STM32F417xx Device Peripheral Access Layer Header File.
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* @brief CMSIS STM32F407xx Device Peripheral Access Layer Header File.
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*
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* This file contains:
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* - Data structures and the address mapping for all peripherals
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@ -43,12 +43,12 @@
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* @{
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*/
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/** @addtogroup stm32f417xx
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/** @addtogroup stm32f407xx
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* @{
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*/
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#ifndef __STM32F417xx_H
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#define __STM32F417xx_H
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#ifndef __STM32F407xx_H
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#define __STM32F407xx_H
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#ifdef __cplusplus
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extern "C" {
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@ -170,10 +170,11 @@ typedef enum
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OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
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OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
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DCMI_IRQn = 78, /*!< DCMI global interrupt */
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CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
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HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
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RNG_IRQn = 80, /*!< RNG global Interrupt */
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FPU_IRQn = 81 /*!< FPU global interrupt */
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} IRQn_Type;
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/* Legacy define */
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#define HASH_RNG_IRQn RNG_IRQn
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/**
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* @}
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@ -792,75 +793,6 @@ typedef struct
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__IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
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} WWDG_TypeDef;
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/**
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* @brief Crypto Processor
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*/
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typedef struct
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{
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__IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */
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__IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */
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__IO uint32_t DIN; /*!< CRYP data input register, Address offset: 0x08 */
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__IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */
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__IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */
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__IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */
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__IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */
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__IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */
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__IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */
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__IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */
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__IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */
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__IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */
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__IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */
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__IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */
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__IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */
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__IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */
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__IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */
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__IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */
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__IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */
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__IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */
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__IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */
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__IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */
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__IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */
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__IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */
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__IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */
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__IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */
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__IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */
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__IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */
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__IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */
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__IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */
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__IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */
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__IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */
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__IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */
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__IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */
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__IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */
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__IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */
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} CRYP_TypeDef;
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/**
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* @brief HASH
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*/
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typedef struct
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{
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__IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
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__IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
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__IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
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__IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
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__IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
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__IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
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uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
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__IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
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} HASH_TypeDef;
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/**
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* @brief HASH_DIGEST
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*/
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typedef struct
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{
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__IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
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} HASH_DIGEST_TypeDef;
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/**
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* @brief RNG
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*/
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@ -1101,9 +1033,6 @@ typedef struct
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/*!< AHB2 peripherals */
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#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000UL)
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#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000UL)
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#define HASH_BASE (AHB2PERIPH_BASE + 0x60400UL)
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#define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710UL)
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#define RNG_BASE (AHB2PERIPH_BASE + 0x60800UL)
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/*!< FSMC Bankx registers base address */
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@ -1219,9 +1148,6 @@ typedef struct
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#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
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#define ETH ((ETH_TypeDef *) ETH_BASE)
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#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
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#define CRYP ((CRYP_TypeDef *) CRYP_BASE)
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#define HASH ((HASH_TypeDef *) HASH_BASE)
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#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
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#define RNG ((RNG_TypeDef *) RNG_BASE)
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#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
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#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
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@ -5523,114 +5449,6 @@ typedef struct
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#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
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#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
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/******************************************************************************/
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/* */
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/* Crypto Processor */
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/* */
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/******************************************************************************/
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/******************* Bits definition for CRYP_CR register ********************/
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#define CRYP_CR_ALGODIR_Pos (2U)
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#define CRYP_CR_ALGODIR_Msk (0x1UL << CRYP_CR_ALGODIR_Pos) /*!< 0x00000004 */
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#define CRYP_CR_ALGODIR CRYP_CR_ALGODIR_Msk
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#define CRYP_CR_ALGOMODE_Pos (3U)
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#define CRYP_CR_ALGOMODE_Msk (0x10007UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00080038 */
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#define CRYP_CR_ALGOMODE CRYP_CR_ALGOMODE_Msk
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#define CRYP_CR_ALGOMODE_0 (0x00001UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */
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#define CRYP_CR_ALGOMODE_1 (0x00002UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */
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#define CRYP_CR_ALGOMODE_2 (0x00004UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */
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#define CRYP_CR_ALGOMODE_TDES_ECB 0x00000000U
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#define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U)
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#define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
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#define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk
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#define CRYP_CR_ALGOMODE_DES_ECB_Pos (4U)
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#define CRYP_CR_ALGOMODE_DES_ECB_Msk (0x1UL << CRYP_CR_ALGOMODE_DES_ECB_Pos) /*!< 0x00000010 */
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#define CRYP_CR_ALGOMODE_DES_ECB CRYP_CR_ALGOMODE_DES_ECB_Msk
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#define CRYP_CR_ALGOMODE_DES_CBC_Pos (3U)
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#define CRYP_CR_ALGOMODE_DES_CBC_Msk (0x3UL << CRYP_CR_ALGOMODE_DES_CBC_Pos) /*!< 0x00000018 */
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#define CRYP_CR_ALGOMODE_DES_CBC CRYP_CR_ALGOMODE_DES_CBC_Msk
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#define CRYP_CR_ALGOMODE_AES_ECB_Pos (5U)
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#define CRYP_CR_ALGOMODE_AES_ECB_Msk (0x1UL << CRYP_CR_ALGOMODE_AES_ECB_Pos) /*!< 0x00000020 */
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#define CRYP_CR_ALGOMODE_AES_ECB CRYP_CR_ALGOMODE_AES_ECB_Msk
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#define CRYP_CR_ALGOMODE_AES_CBC_Pos (3U)
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#define CRYP_CR_ALGOMODE_AES_CBC_Msk (0x5UL << CRYP_CR_ALGOMODE_AES_CBC_Pos) /*!< 0x00000028 */
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#define CRYP_CR_ALGOMODE_AES_CBC CRYP_CR_ALGOMODE_AES_CBC_Msk
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#define CRYP_CR_ALGOMODE_AES_CTR_Pos (4U)
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#define CRYP_CR_ALGOMODE_AES_CTR_Msk (0x3UL << CRYP_CR_ALGOMODE_AES_CTR_Pos) /*!< 0x00000030 */
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#define CRYP_CR_ALGOMODE_AES_CTR CRYP_CR_ALGOMODE_AES_CTR_Msk
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#define CRYP_CR_ALGOMODE_AES_KEY_Pos (3U)
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#define CRYP_CR_ALGOMODE_AES_KEY_Msk (0x7UL << CRYP_CR_ALGOMODE_AES_KEY_Pos) /*!< 0x00000038 */
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#define CRYP_CR_ALGOMODE_AES_KEY CRYP_CR_ALGOMODE_AES_KEY_Msk
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#define CRYP_CR_DATATYPE_Pos (6U)
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#define CRYP_CR_DATATYPE_Msk (0x3UL << CRYP_CR_DATATYPE_Pos) /*!< 0x000000C0 */
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#define CRYP_CR_DATATYPE CRYP_CR_DATATYPE_Msk
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#define CRYP_CR_DATATYPE_0 (0x1UL << CRYP_CR_DATATYPE_Pos) /*!< 0x00000040 */
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#define CRYP_CR_DATATYPE_1 (0x2UL << CRYP_CR_DATATYPE_Pos) /*!< 0x00000080 */
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#define CRYP_CR_KEYSIZE_Pos (8U)
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#define CRYP_CR_KEYSIZE_Msk (0x3UL << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000300 */
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#define CRYP_CR_KEYSIZE CRYP_CR_KEYSIZE_Msk
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#define CRYP_CR_KEYSIZE_0 (0x1UL << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000100 */
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#define CRYP_CR_KEYSIZE_1 (0x2UL << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000200 */
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#define CRYP_CR_FFLUSH_Pos (14U)
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#define CRYP_CR_FFLUSH_Msk (0x1UL << CRYP_CR_FFLUSH_Pos) /*!< 0x00004000 */
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#define CRYP_CR_FFLUSH CRYP_CR_FFLUSH_Msk
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#define CRYP_CR_CRYPEN_Pos (15U)
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#define CRYP_CR_CRYPEN_Msk (0x1UL << CRYP_CR_CRYPEN_Pos) /*!< 0x00008000 */
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#define CRYP_CR_CRYPEN CRYP_CR_CRYPEN_Msk
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#define CRYP_CR_GCM_CCMPH_Pos (16U)
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#define CRYP_CR_GCM_CCMPH_Msk (0x3UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00030000 */
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#define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk
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#define CRYP_CR_GCM_CCMPH_0 (0x1UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */
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#define CRYP_CR_GCM_CCMPH_1 (0x2UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */
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#define CRYP_CR_ALGOMODE_3 0x00080000U
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/****************** Bits definition for CRYP_SR register *********************/
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#define CRYP_SR_IFEM_Pos (0U)
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#define CRYP_SR_IFEM_Msk (0x1UL << CRYP_SR_IFEM_Pos) /*!< 0x00000001 */
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#define CRYP_SR_IFEM CRYP_SR_IFEM_Msk
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#define CRYP_SR_IFNF_Pos (1U)
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#define CRYP_SR_IFNF_Msk (0x1UL << CRYP_SR_IFNF_Pos) /*!< 0x00000002 */
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#define CRYP_SR_IFNF CRYP_SR_IFNF_Msk
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#define CRYP_SR_OFNE_Pos (2U)
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#define CRYP_SR_OFNE_Msk (0x1UL << CRYP_SR_OFNE_Pos) /*!< 0x00000004 */
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#define CRYP_SR_OFNE CRYP_SR_OFNE_Msk
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#define CRYP_SR_OFFU_Pos (3U)
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#define CRYP_SR_OFFU_Msk (0x1UL << CRYP_SR_OFFU_Pos) /*!< 0x00000008 */
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#define CRYP_SR_OFFU CRYP_SR_OFFU_Msk
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#define CRYP_SR_BUSY_Pos (4U)
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#define CRYP_SR_BUSY_Msk (0x1UL << CRYP_SR_BUSY_Pos) /*!< 0x00000010 */
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#define CRYP_SR_BUSY CRYP_SR_BUSY_Msk
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/****************** Bits definition for CRYP_DMACR register ******************/
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#define CRYP_DMACR_DIEN_Pos (0U)
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#define CRYP_DMACR_DIEN_Msk (0x1UL << CRYP_DMACR_DIEN_Pos) /*!< 0x00000001 */
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#define CRYP_DMACR_DIEN CRYP_DMACR_DIEN_Msk
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#define CRYP_DMACR_DOEN_Pos (1U)
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#define CRYP_DMACR_DOEN_Msk (0x1UL << CRYP_DMACR_DOEN_Pos) /*!< 0x00000002 */
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#define CRYP_DMACR_DOEN CRYP_DMACR_DOEN_Msk
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/***************** Bits definition for CRYP_IMSCR register ******************/
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#define CRYP_IMSCR_INIM_Pos (0U)
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#define CRYP_IMSCR_INIM_Msk (0x1UL << CRYP_IMSCR_INIM_Pos) /*!< 0x00000001 */
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#define CRYP_IMSCR_INIM CRYP_IMSCR_INIM_Msk
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#define CRYP_IMSCR_OUTIM_Pos (1U)
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#define CRYP_IMSCR_OUTIM_Msk (0x1UL << CRYP_IMSCR_OUTIM_Pos) /*!< 0x00000002 */
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#define CRYP_IMSCR_OUTIM CRYP_IMSCR_OUTIM_Msk
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/****************** Bits definition for CRYP_RISR register *******************/
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#define CRYP_RISR_OUTRIS_Pos (0U)
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#define CRYP_RISR_OUTRIS_Msk (0x1UL << CRYP_RISR_OUTRIS_Pos) /*!< 0x00000001 */
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#define CRYP_RISR_OUTRIS CRYP_RISR_OUTRIS_Msk
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#define CRYP_RISR_INRIS_Pos (1U)
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#define CRYP_RISR_INRIS_Msk (0x1UL << CRYP_RISR_INRIS_Pos) /*!< 0x00000002 */
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#define CRYP_RISR_INRIS CRYP_RISR_INRIS_Msk
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/****************** Bits definition for CRYP_MISR register *******************/
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#define CRYP_MISR_INMIS_Pos (0U)
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#define CRYP_MISR_INMIS_Msk (0x1UL << CRYP_MISR_INMIS_Pos) /*!< 0x00000001 */
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#define CRYP_MISR_INMIS CRYP_MISR_INMIS_Msk
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#define CRYP_MISR_OUTMIS_Pos (1U)
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#define CRYP_MISR_OUTMIS_Msk (0x1UL << CRYP_MISR_OUTMIS_Pos) /*!< 0x00000002 */
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#define CRYP_MISR_OUTMIS CRYP_MISR_OUTMIS_Msk
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/******************************************************************************/
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/* */
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/* Digital to Analog Converter */
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#define DCMI_CR_FCRC_1 0x00000200U
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#define DCMI_CR_EDM_0 0x00000400U
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#define DCMI_CR_EDM_1 0x00000800U
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#define DCMI_CR_CRE_Pos (12U)
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#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
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#define DCMI_CR_CRE DCMI_CR_CRE_Msk
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#define DCMI_CR_ENABLE_Pos (14U)
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#define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */
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#define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
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#define FSMC_BWTR4_DATAST_Pos (8U)
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#define FSMC_BWTR4_DATAST_Msk (0xFFUL << FSMC_BWTR4_DATAST_Pos) /*!< 0x0000FF00 */
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#define FSMC_BWTR4_DATAST FSMC_BWTR4_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
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#define FSMC_BWTR4_DATAST FSMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
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#define FSMC_BWTR4_DATAST_0 0x00000100U /*!<Bit 0 */
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#define FSMC_BWTR4_DATAST_1 0x00000200U /*!<Bit 1 */
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#define FSMC_BWTR4_DATAST_2 0x00000400U /*!<Bit 2 */
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#define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
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/******************************************************************************/
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/* */
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/* HASH */
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/* */
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/******************************************************************************/
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/****************** Bits definition for HASH_CR register ********************/
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#define HASH_CR_INIT_Pos (2U)
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#define HASH_CR_INIT_Msk (0x1UL << HASH_CR_INIT_Pos) /*!< 0x00000004 */
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#define HASH_CR_INIT HASH_CR_INIT_Msk
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#define HASH_CR_DMAE_Pos (3U)
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#define HASH_CR_DMAE_Msk (0x1UL << HASH_CR_DMAE_Pos) /*!< 0x00000008 */
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#define HASH_CR_DMAE HASH_CR_DMAE_Msk
|
||||
#define HASH_CR_DATATYPE_Pos (4U)
|
||||
#define HASH_CR_DATATYPE_Msk (0x3UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000030 */
|
||||
#define HASH_CR_DATATYPE HASH_CR_DATATYPE_Msk
|
||||
#define HASH_CR_DATATYPE_0 (0x1UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000010 */
|
||||
#define HASH_CR_DATATYPE_1 (0x2UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000020 */
|
||||
#define HASH_CR_MODE_Pos (6U)
|
||||
#define HASH_CR_MODE_Msk (0x1UL << HASH_CR_MODE_Pos) /*!< 0x00000040 */
|
||||
#define HASH_CR_MODE HASH_CR_MODE_Msk
|
||||
#define HASH_CR_ALGO_Pos (7U)
|
||||
#define HASH_CR_ALGO_Msk (0x1UL << HASH_CR_ALGO_Pos) /*!< 0x00000080 */
|
||||
#define HASH_CR_ALGO HASH_CR_ALGO_Msk
|
||||
#define HASH_CR_ALGO_0 (0x1UL << HASH_CR_ALGO_Pos) /*!< 0x00000080 */
|
||||
#define HASH_CR_NBW_Pos (8U)
|
||||
#define HASH_CR_NBW_Msk (0xFUL << HASH_CR_NBW_Pos) /*!< 0x00000F00 */
|
||||
#define HASH_CR_NBW HASH_CR_NBW_Msk
|
||||
#define HASH_CR_NBW_0 (0x1UL << HASH_CR_NBW_Pos) /*!< 0x00000100 */
|
||||
#define HASH_CR_NBW_1 (0x2UL << HASH_CR_NBW_Pos) /*!< 0x00000200 */
|
||||
#define HASH_CR_NBW_2 (0x4UL << HASH_CR_NBW_Pos) /*!< 0x00000400 */
|
||||
#define HASH_CR_NBW_3 (0x8UL << HASH_CR_NBW_Pos) /*!< 0x00000800 */
|
||||
#define HASH_CR_DINNE_Pos (12U)
|
||||
#define HASH_CR_DINNE_Msk (0x1UL << HASH_CR_DINNE_Pos) /*!< 0x00001000 */
|
||||
#define HASH_CR_DINNE HASH_CR_DINNE_Msk
|
||||
#define HASH_CR_LKEY_Pos (16U)
|
||||
#define HASH_CR_LKEY_Msk (0x1UL << HASH_CR_LKEY_Pos) /*!< 0x00010000 */
|
||||
#define HASH_CR_LKEY HASH_CR_LKEY_Msk
|
||||
|
||||
/****************** Bits definition for HASH_STR register *******************/
|
||||
#define HASH_STR_NBLW_Pos (0U)
|
||||
#define HASH_STR_NBLW_Msk (0x1FUL << HASH_STR_NBLW_Pos) /*!< 0x0000001F */
|
||||
#define HASH_STR_NBLW HASH_STR_NBLW_Msk
|
||||
#define HASH_STR_NBLW_0 (0x01UL << HASH_STR_NBLW_Pos) /*!< 0x00000001 */
|
||||
#define HASH_STR_NBLW_1 (0x02UL << HASH_STR_NBLW_Pos) /*!< 0x00000002 */
|
||||
#define HASH_STR_NBLW_2 (0x04UL << HASH_STR_NBLW_Pos) /*!< 0x00000004 */
|
||||
#define HASH_STR_NBLW_3 (0x08UL << HASH_STR_NBLW_Pos) /*!< 0x00000008 */
|
||||
#define HASH_STR_NBLW_4 (0x10UL << HASH_STR_NBLW_Pos) /*!< 0x00000010 */
|
||||
#define HASH_STR_DCAL_Pos (8U)
|
||||
#define HASH_STR_DCAL_Msk (0x1UL << HASH_STR_DCAL_Pos) /*!< 0x00000100 */
|
||||
#define HASH_STR_DCAL HASH_STR_DCAL_Msk
|
||||
/* Aliases for HASH_STR register */
|
||||
#define HASH_STR_NBW HASH_STR_NBLW
|
||||
#define HASH_STR_NBW_0 HASH_STR_NBLW_0
|
||||
#define HASH_STR_NBW_1 HASH_STR_NBLW_1
|
||||
#define HASH_STR_NBW_2 HASH_STR_NBLW_2
|
||||
#define HASH_STR_NBW_3 HASH_STR_NBLW_3
|
||||
#define HASH_STR_NBW_4 HASH_STR_NBLW_4
|
||||
|
||||
/****************** Bits definition for HASH_IMR register *******************/
|
||||
#define HASH_IMR_DINIE_Pos (0U)
|
||||
#define HASH_IMR_DINIE_Msk (0x1UL << HASH_IMR_DINIE_Pos) /*!< 0x00000001 */
|
||||
#define HASH_IMR_DINIE HASH_IMR_DINIE_Msk
|
||||
#define HASH_IMR_DCIE_Pos (1U)
|
||||
#define HASH_IMR_DCIE_Msk (0x1UL << HASH_IMR_DCIE_Pos) /*!< 0x00000002 */
|
||||
#define HASH_IMR_DCIE HASH_IMR_DCIE_Msk
|
||||
/* Aliases for HASH_IMR register */
|
||||
#define HASH_IMR_DINIM HASH_IMR_DINIE
|
||||
#define HASH_IMR_DCIM HASH_IMR_DCIE
|
||||
|
||||
/****************** Bits definition for HASH_SR register ********************/
|
||||
#define HASH_SR_DINIS_Pos (0U)
|
||||
#define HASH_SR_DINIS_Msk (0x1UL << HASH_SR_DINIS_Pos) /*!< 0x00000001 */
|
||||
#define HASH_SR_DINIS HASH_SR_DINIS_Msk
|
||||
#define HASH_SR_DCIS_Pos (1U)
|
||||
#define HASH_SR_DCIS_Msk (0x1UL << HASH_SR_DCIS_Pos) /*!< 0x00000002 */
|
||||
#define HASH_SR_DCIS HASH_SR_DCIS_Msk
|
||||
#define HASH_SR_DMAS_Pos (2U)
|
||||
#define HASH_SR_DMAS_Msk (0x1UL << HASH_SR_DMAS_Pos) /*!< 0x00000004 */
|
||||
#define HASH_SR_DMAS HASH_SR_DMAS_Msk
|
||||
#define HASH_SR_BUSY_Pos (3U)
|
||||
#define HASH_SR_BUSY_Msk (0x1UL << HASH_SR_BUSY_Pos) /*!< 0x00000008 */
|
||||
#define HASH_SR_BUSY HASH_SR_BUSY_Msk
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
/* Inter-integrated Circuit Interface */
|
||||
|
|
@ -10030,14 +9768,6 @@ typedef struct
|
|||
#define RCC_AHB2RSTR_DCMIRST_Pos (0U)
|
||||
#define RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */
|
||||
#define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
|
||||
#define RCC_AHB2RSTR_CRYPRST_Pos (4U)
|
||||
#define RCC_AHB2RSTR_CRYPRST_Msk (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos) /*!< 0x00000010 */
|
||||
#define RCC_AHB2RSTR_CRYPRST RCC_AHB2RSTR_CRYPRST_Msk
|
||||
#define RCC_AHB2RSTR_HASHRST_Pos (5U)
|
||||
#define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00000020 */
|
||||
#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk
|
||||
/* maintained for legacy purpose */
|
||||
#define RCC_AHB2RSTR_HSAHRST RCC_AHB2RSTR_HASHRST
|
||||
#define RCC_AHB2RSTR_RNGRST_Pos (6U)
|
||||
#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
|
||||
#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
|
||||
|
|
@ -10229,12 +9959,6 @@ typedef struct
|
|||
#define RCC_AHB2ENR_DCMIEN_Pos (0U)
|
||||
#define RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */
|
||||
#define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
|
||||
#define RCC_AHB2ENR_CRYPEN_Pos (4U)
|
||||
#define RCC_AHB2ENR_CRYPEN_Msk (0x1UL << RCC_AHB2ENR_CRYPEN_Pos) /*!< 0x00000010 */
|
||||
#define RCC_AHB2ENR_CRYPEN RCC_AHB2ENR_CRYPEN_Msk
|
||||
#define RCC_AHB2ENR_HASHEN_Pos (5U)
|
||||
#define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00000020 */
|
||||
#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk
|
||||
#define RCC_AHB2ENR_RNGEN_Pos (6U)
|
||||
#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
|
||||
#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
|
||||
|
|
@ -10437,12 +10161,6 @@ typedef struct
|
|||
#define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
|
||||
#define RCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
|
||||
#define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
|
||||
#define RCC_AHB2LPENR_CRYPLPEN_Pos (4U)
|
||||
#define RCC_AHB2LPENR_CRYPLPEN_Msk (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */
|
||||
#define RCC_AHB2LPENR_CRYPLPEN RCC_AHB2LPENR_CRYPLPEN_Msk
|
||||
#define RCC_AHB2LPENR_HASHLPEN_Pos (5U)
|
||||
#define RCC_AHB2LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */
|
||||
#define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk
|
||||
#define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
|
||||
#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
|
||||
#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
|
||||
|
|
@ -11919,6 +11637,8 @@ typedef struct
|
|||
#define SYSCFG_PMC_MII_RMII_SEL_Pos (23U)
|
||||
#define SYSCFG_PMC_MII_RMII_SEL_Msk (0x1UL << SYSCFG_PMC_MII_RMII_SEL_Pos) /*!< 0x00800000 */
|
||||
#define SYSCFG_PMC_MII_RMII_SEL SYSCFG_PMC_MII_RMII_SEL_Msk /*!<Ethernet PHY interface selection */
|
||||
/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
|
||||
#define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
|
||||
#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
|
||||
|
|
@ -15470,9 +15190,6 @@ typedef struct
|
|||
((INSTANCE) == TIM13)|| \
|
||||
((INSTANCE) == TIM14))
|
||||
|
||||
/****************** TIM Instances : supporting synchronization ****************/
|
||||
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
|
||||
|
||||
/************* TIM Instances : at least 1 capture/compare channel *************/
|
||||
#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
|
|
@ -15578,6 +15295,10 @@ typedef struct
|
|||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM9) || \
|
||||
((INSTANCE) == TIM12))
|
||||
|
||||
/****************** TIM Instances : supporting synchronization ****************/
|
||||
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
|
||||
|
||||
/********************** TIM Instances : 32 bit Counter ************************/
|
||||
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM5))
|
||||
|
|
@ -15886,7 +15607,7 @@ typedef struct
|
|||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* __STM32F417xx_H */
|
||||
#endif /* __STM32F407xx_H */
|
||||
|
||||
|
||||
|
||||
Loading…
Add table
Add a link
Reference in a new issue