This commit is contained in:
Attila Body 2020-02-10 15:06:45 +01:00
parent 90d89c7fbe
commit 49383b1b32
68 changed files with 3385 additions and 610 deletions

View file

@ -24,7 +24,7 @@
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<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Src"/>
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Startup"/> <entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Startup"/>
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="components"/> <entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="App"/>
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Src"/>
<entry excluding="test" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="platforms"/> <entry excluding="test" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="platforms"/>
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="components"/>
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Drivers"/>
</sourceEntries> </sourceEntries>
</configuration> </configuration>
</storageModule> </storageModule>

1
.gitignore vendored
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@ -1,6 +1,7 @@
Release/ Release/
Debug/ Debug/
.ino.cpp .ino.cpp
*.launch
*.d *.d
*.bak *.bak
*.tmp *.tmp

File diff suppressed because one or more lines are too long

66
App/application.cpp Normal file
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@ -0,0 +1,66 @@
/*
* mainloop.cpp
*
* Created on: Sep 11, 2019
* Author: abody
*/
#include <ili9341.h>
#include <application.h>
#include <initializer_list>
#include "main.h"
#include "globals.h"
#define BORDER 60
#define BARWIDTH 2
void MainLoop()
{
Application m;
m.Loop();
}
Application::Application()
: GlobalsInitializer(&m_console)
, m_console(USART1, DMA2, LL_DMA_STREAM_2, LL_DMA_STREAM_7, this, nullptr)
{
}
void Application::Loop()
{
//LL_SYSTICK_EnableIT();
Ili9341Fsmc &lcd(Ili9341Fsmc::Init(nullptr, nullptr, DMA2, LL_DMA_STREAM_4, false));
lcd.FillRect(Ili9341Fsmc::ILI9341_BLACK, false);
//lcd.Test();
lcd.SetCursor( 10, 10, Ili9341Fsmc::ILI9341_WHITE, Ili9341Fsmc::ILI9341_BLACK);
lcd.Print("Baszod");
for(;;) {
if(m_received && m_transmitted) {
m_transmitted = false;
m_console.SendLine(reinterpret_cast<char*>(const_cast<char*>(m_rcvdBuffer->buffer)), m_rcvdBuffer->len);
m_received = false;
m_rcvdBuffer->busy = false;
}
}
//LL_GPIO_TogglePin(LED1_GPIO_Port, LED1_Pin);
//LL_GPIO_TogglePin(LED2_GPIO_Port, LED2_Pin);
//LL_mDelay(25);
}
void Application::LineReceived(void *userParam, SerialConsole<257>::Buffer *buffer)
{
m_received = true;
m_rcvdBuffer = buffer;
}
void Application::TransmissionComplete(void *userParam, SerialConsole<257>::Buffer *buffer)
{
m_transmitted = true;
}

49
App/application.h Normal file
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@ -0,0 +1,49 @@
/*
* mainloop.h
*
* Created on: Sep 11, 2019
* Author: abody
*/
#ifndef MAINLOOP_H_
#define MAINLOOP_H_
#if defined(__cplusplus)
extern "C" {
#endif
void MainLoop();
#if defined(__cplusplus)
}
#endif
#if defined(__cplusplus)
#include <f4ll_cpp/serialconsole.h>
#include "globals.h"
struct GlobalsInitializer {
GlobalsInitializer(SerialConsole<257> *console) {
g_console = console;
}
};
class Application : public GlobalsInitializer, public SerialConsole<257>::ISerialConsoleCallback {
public:
Application();
void Loop();
private:
virtual void LineReceived(void *userParam, SerialConsole<257>::Buffer *buffer);
virtual void TransmissionComplete(void *userParam, SerialConsole<257>::Buffer *buffer);
SerialConsole<257> m_console;
volatile bool m_received = false;
volatile SerialConsole<257>::Buffer *m_rcvdBuffer;
volatile bool m_transmitted = true;
};
#endif // __cplusplus
#endif /* MAINLOOP_H_ */

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@ -7,3 +7,4 @@
#include "globals.h" #include "globals.h"
SerialConsole<257> *g_console = nullptr;

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@ -7,5 +7,12 @@
#ifndef GLOBALS_H_ #ifndef GLOBALS_H_
#define GLOBALS_H_ #define GLOBALS_H_
#include <f4ll_cpp/serialconsole.h>
#if defined(__cplusplus)
extern SerialConsole<257> *g_console;
#endif // __cplusplus
#endif /* GLOBALS_H_ */ #endif /* GLOBALS_H_ */

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@ -18,10 +18,9 @@
Ili9341Fsmc::Ili9341Fsmc(volatile uint16_t *reg, volatile uint16_t *ram, Ili9341Fsmc::Ili9341Fsmc(volatile uint16_t *reg, volatile uint16_t *ram,
DMA_TypeDef *dma, uint32_t dmaStream, DMA_TypeDef *dma, uint32_t dmaStream,
bool horizontal) bool horizontal)
: m_reg(reg ? reg : (volatile unsigned short *) 0x60000000) : DmaHelper(dma, dmaStream)
, m_reg(reg ? reg : (volatile unsigned short *) 0x60000000)
, m_ram(ram ? ram : (volatile unsigned short *) 0x60080000) , m_ram(ram ? ram : (volatile unsigned short *) 0x60080000)
, m_dma(dma)
, m_dmaStream(dmaStream)
, m_width(horizontal ? LCD_L : LCD_S) , m_width(horizontal ? LCD_L : LCD_S)
, m_height(horizontal ? LCD_S : LCD_L) , m_height(horizontal ? LCD_S : LCD_L)
, m_rectX(0) , m_rectX(0)
@ -29,8 +28,8 @@ Ili9341Fsmc::Ili9341Fsmc(volatile uint16_t *reg, volatile uint16_t *ram,
, m_rectWidth(m_width) , m_rectWidth(m_width)
, m_rectHeight(m_height) , m_rectHeight(m_height)
{ {
LL_DMA_EnableIT_TC(m_dma, m_dmaStream); LL_DMA_EnableIT_TC(GetDma(), GetStream());
LL_DMA_EnableIT_TE(m_dma, m_dmaStream); LL_DMA_EnableIT_TE(GetDma(), GetStream());
WriteCmd(ILI9341_RESET); WriteCmd(ILI9341_RESET);
HAL_Delay(10); HAL_Delay(10);
@ -84,7 +83,7 @@ void Ili9341Fsmc::SetRect(uint16_t x, uint16_t y, uint16_t width, uint16_t heigh
if(x > m_width || y > m_height || !width || !height ) if(x > m_width || y > m_height || !width || !height )
return; return;
WaitDmaIddle(); WaitDmaIdle();
m_rectX = x; m_rectX = x;
m_rectY = y; m_rectY = y;
@ -98,66 +97,203 @@ void Ili9341Fsmc::SetRect(uint16_t x, uint16_t y, uint16_t width, uint16_t heigh
WriteCmd(ILI9341_PAGE_ADDR, {(uint16_t)(y >> 8), (uint16_t)(y & 0xff), (uint16_t)(bottom >> 8), (uint16_t)(bottom & 0xff)}); WriteCmd(ILI9341_PAGE_ADDR, {(uint16_t)(y >> 8), (uint16_t)(y & 0xff), (uint16_t)(bottom >> 8), (uint16_t)(bottom & 0xff)});
} }
void Ili9341Fsmc::FillRect(uint16_t color) void Ili9341Fsmc::FillRect(uint16_t color, bool async)
{ {
uint32_t count = m_rectWidth * m_rectHeight; uint32_t count = m_rectWidth * m_rectHeight;
WaitDmaIddle(); WaitDmaIdle();
m_dmaColor = color; m_dmaColor = color;
WriteCmd(ILI9341_GRAM); WriteCmd(ILI9341_GRAM);
LL_DMA_SetM2MDstAddress(m_dma, m_dmaStream, (uint32_t)m_ram); LL_DMA_SetM2MDstAddress(GetDma(), GetStream(), (uint32_t)m_ram);
LL_DMA_SetM2MSrcAddress(m_dma, m_dmaStream, (uint32_t) &m_dmaColor); LL_DMA_SetM2MSrcAddress(GetDma(), GetStream(), (uint32_t) &m_dmaColor);
LL_DMA_SetMemoryIncMode(m_dma, m_dmaStream, LL_DMA_MEMORY_NOINCREMENT); LL_DMA_SetMemoryIncMode(GetDma(), GetStream(), LL_DMA_MEMORY_NOINCREMENT);
LL_DMA_SetPeriphIncMode(m_dma, m_dmaStream, LL_DMA_PERIPH_NOINCREMENT); LL_DMA_SetPeriphIncMode(GetDma(), GetStream(), LL_DMA_PERIPH_NOINCREMENT);
SetupDmaSize(count); SetupDmaSize(count);
m_dmaEngineBusy = true; m_dmaEngineBusy = true;
LL_DMA_EnableStream(m_dma, m_dmaStream); LL_DMA_EnableStream(GetDma(), GetStream());
if(!async)
// for(uint32_t pix = 0; pix < count; ++pix) WaitDmaIdle();
// *m_ram = color;
} }
void Ili9341Fsmc::FillRect(uint16_t x, uint16_t y, uint16_t width, uint16_t height, uint16_t color) void Ili9341Fsmc::FillRect(uint16_t x, uint16_t y, uint16_t width, uint16_t height, uint16_t color, bool async)
{ {
SetRect(x, y, width, height); SetRect(x, y, width, height);
FillRect(color); FillRect(color, async);
} }
void Ili9341Fsmc::SetupDmaSize(uint32_t size) void Ili9341Fsmc::SetupDmaSize(uint32_t size)
{ {
if(size > 0xffff) { if(size > 0xffff) {
LL_DMA_SetDataLength(m_dma, m_dmaStream, 0xffff); LL_DMA_SetDataLength(GetDma(), GetStream(), 0xffff);
m_dmaRemainingPixels = size - 0xffff; m_dmaRemainingPixels = size - 0xffff;
} else { } else {
LL_DMA_SetDataLength(m_dma, m_dmaStream, size); LL_DMA_SetDataLength(GetDma(), GetStream(), size);
m_dmaRemainingPixels = 0; m_dmaRemainingPixels = 0;
} }
} }
void Ili9341Fsmc::DmaTransferComplete() void Ili9341Fsmc::HandleDmaIrq()
{ {
if(!m_dmaRemainingPixels) if(*GetIsReg() & GetTcMask()) { //LL_DMA_IsActiveFlag_TC4(DMA2)) {
m_dmaEngineBusy = false; *GetIfcReg() = GetTcMask(); //LL_DMA_ClearFlag_TC4(DMA2);
else { LL_DMA_DisableStream(GetDma(), GetStream());
SetupDmaSize(m_dmaRemainingPixels); if(!m_dmaRemainingPixels)
LL_DMA_EnableStream(m_dma, m_dmaStream); m_dmaEngineBusy = false;
} else {
SetupDmaSize(m_dmaRemainingPixels);
LL_DMA_EnableStream(GetDma(), GetStream());
}
} else if(*GetIsReg() & GetTeMask())
*GetIfcReg() = GetTeMask();
} }
void Ili9341Fsmc::Test() void Ili9341Fsmc::SetCursor(uint16_t x, uint16_t y, uint16_t fgColor, uint16_t bgColor)
{ {
FillRect(ILI9341_PINK); m_xPos = x;
WaitDmaIddle(); m_yPos = y;
m_fgColor = fgColor;
m_bgColor = bgColor;
}
void Ili9341Fsmc::PrintChar(char c)
{
if(m_xPos >= m_width - CHRWIDTH || m_yPos >= m_height - CHRHEIGHT || c < ' ' || c >= '~')
return;
uint8_t const *chrPtr = m_font[c - 32];
SetRect(m_xPos, m_yPos, CHRWIDTH, CHRHEIGHT);
WriteCmd(ILI9341_GRAM);
for(uint8_t y = 0; y < CHRWIDTH; ++y ) {
uint8_t mask = 0x80;
for(uint8_t x = 0; x < CHRHEIGHT; ++x)
*m_ram = (chrPtr[x] & mask) ? m_fgColor : m_fgColor;
mask >>= 1;
}
m_xPos += CHRHEIGHT;
}
void Ili9341Fsmc::PrintChar(char c, uint16_t x, uint16_t y, uint16_t fgColor, uint16_t bgColor)
{
SetCursor(x, y, fgColor, bgColor);
PrintChar(c);
}
void Ili9341Fsmc::Print(char const *str, uint8_t len)
{
if(!len)
len = strlen(str);
while(len--)
PrintChar(*str++);
}
void Ili9341Fsmc::Test() {
FillRect(ILI9341_PINK, false);
WriteCmd(ILI9341_GRAM); WriteCmd(ILI9341_GRAM);
uint16_t fillers[4] = { 0xf800, 0x7e0, 0x1f, 0xffff }; uint16_t fillers[4] = { 0xf800, 0x7e0, 0x1f, 0xffff };
for(uint32_t y = 0; y < m_height; ++y) { for(uint32_t y = 0; y < m_height; ++y) {
uint32_t x; uint32_t x;
for(x = 0; x < m_width / 2; ++x) { for(x = 0; x < m_width / 2; ++x)
*m_ram = fillers[ (x&0x18) >> 3 ]; *m_ram = fillers[ (x&0x18) >> 3 ];
} for( ; x < m_width; ++x)
for( ; x < m_width; ++x) {
*m_ram = 0; *m_ram = 0;
}
} }
} }
const uint8_t Ili9341Fsmc::m_font[CHRCOUNT][CHRWIDTH] = {
{0x00,0x00,0x00,0x00,0x00,0x00}, //
{0x2f,0x00,0x00,0x00,0x00,0x00}, // !
{0x03,0x00,0x03,0x00,0x00,0x00}, // "
{0x12,0x3f,0x12,0x12,0x3f,0x12}, // #
{0x2e,0x2a,0x7f,0x2a,0x3a,0x00}, // $
{0x23,0x13,0x08,0x04,0x32,0x31}, // %
{0x10,0x2a,0x25,0x2a,0x10,0x20}, // &
{0x02,0x01,0x00,0x00,0x00,0x00}, // '
{0x1e,0x21,0x00,0x00,0x00,0x00}, // (
{0x21,0x1e,0x00,0x00,0x00,0x00}, // )
{0x08,0x2a,0x1c,0x2a,0x08,0x08}, // *
{0x08,0x08,0x3e,0x08,0x08,0x08}, // +
{0x80,0x60,0x00,0x00,0x00,0x00}, // ,
{0x08,0x08,0x08,0x08,0x08,0x00}, // -
{0x30,0x30,0x00,0x00,0x00,0x00}, // .
{0x20,0x10,0x08,0x04,0x02,0x00}, // /
{0x1e,0x31,0x29,0x25,0x23,0x1e}, // 0
{0x22,0x21,0x3f,0x20,0x20,0x20}, // 1
{0x32,0x29,0x29,0x29,0x29,0x26}, // 2
{0x12,0x21,0x21,0x25,0x25,0x1a}, // 3
{0x18,0x14,0x12,0x3f,0x10,0x10}, // 4
{0x17,0x25,0x25,0x25,0x25,0x19}, // 5
{0x1e,0x25,0x25,0x25,0x25,0x18}, // 6
{0x01,0x01,0x31,0x09,0x05,0x03}, // 7
{0x1a,0x25,0x25,0x25,0x25,0x1a}, // 8
{0x06,0x29,0x29,0x29,0x29,0x1e}, // 9
{0x24,0x00,0x00,0x00,0x00,0x00}, // :
{0x80,0x64,0x00,0x00,0x00,0x00}, // ;
{0x08,0x14,0x22,0x00,0x00,0x00}, // <
{0x14,0x14,0x14,0x14,0x14,0x00}, // =
{0x22,0x14,0x08,0x00,0x00,0x00}, // >
{0x02,0x01,0x01,0x29,0x05,0x02}, // ?
{0x1e,0x21,0x2d,0x2b,0x2d,0x0e}, // @
{0x3e,0x09,0x09,0x09,0x09,0x3e}, // A
{0x3f,0x25,0x25,0x25,0x25,0x1a}, // B
{0x1e,0x21,0x21,0x21,0x21,0x12}, // C
{0x3f,0x21,0x21,0x21,0x12,0x0c}, // D
{0x3f,0x25,0x25,0x25,0x25,0x21}, // E
{0x3f,0x05,0x05,0x05,0x05,0x01}, // F
{0x1e,0x21,0x21,0x21,0x29,0x1a}, // G
{0x3f,0x04,0x04,0x04,0x04,0x3f}, // H
{0x21,0x21,0x3f,0x21,0x21,0x21}, // I
{0x10,0x20,0x20,0x20,0x20,0x1f}, // J
{0x3f,0x04,0x0c,0x0a,0x11,0x20}, // K
{0x3f,0x20,0x20,0x20,0x20,0x20}, // L
{0x3f,0x02,0x04,0x04,0x02,0x3f}, // M
{0x3f,0x02,0x04,0x08,0x10,0x3f}, // N
{0x1e,0x21,0x21,0x21,0x21,0x1e}, // O
{0x3f,0x09,0x09,0x09,0x09,0x06}, // P
{0x1e,0x21,0x29,0x31,0x21,0x1e}, // Q
{0x3f,0x09,0x09,0x09,0x19,0x26}, // R
{0x12,0x25,0x25,0x25,0x25,0x18}, // S
{0x01,0x01,0x01,0x3f,0x01,0x01}, // T
{0x1f,0x20,0x20,0x20,0x20,0x1f}, // U
{0x0f,0x10,0x20,0x20,0x10,0x0f}, // V
{0x1f,0x20,0x10,0x10,0x20,0x1f}, // W
{0x21,0x12,0x0c,0x0c,0x12,0x21}, // X
{0x01,0x02,0x0c,0x38,0x04,0x02}, // Y
{0x21,0x31,0x29,0x25,0x23,0x21}, // Z
{0x3f,0x21,0x00,0x00,0x00,0x00}, // [
{0x02,0x04,0x08,0x10,0x20,0x00}, // "\"
{0x21,0x3f,0x00,0x00,0x00,0x00}, // ]
{0x04,0x02,0x3f,0x02,0x04,0x00}, // ^
{0x40,0x40,0x40,0x40,0x40,0x40}, // _
{0x01,0x02,0x00,0x00,0x00,0x00}, // `
{0x10,0x30,0x2a,0x2a,0x3c,0x00}, // a
{0x3f,0x24,0x24,0x24,0x18,0x00}, // b
{0x0c,0x14,0x22,0x22,0x00,0x00}, // c
{0x18,0x24,0x24,0x24,0x3f,0x00}, // d
{0x1c,0x2c,0x2a,0x2a,0x24,0x00}, // e
{0x3e,0x05,0x01,0x00,0x00,0x00}, // f
{0x18,0x28,0xa4,0xa4,0x7c,0x00}, // g
{0x3f,0x04,0x04,0x0c,0x30,0x00}, // h
{0x24,0x3d,0x20,0x00,0x00,0x00}, // i
{0x20,0x40,0x40,0x3d,0x00,0x00}, // j
{0x3f,0x0c,0x12,0x20,0x00,0x00}, // k
{0x1f,0x20,0x20,0x00,0x00,0x00}, // l
{0x3e,0x02,0x3c,0x02,0x3c,0x00}, // m
{0x3e,0x02,0x02,0x02,0x3c,0x00}, // n
{0x0c,0x14,0x22,0x32,0x0c,0x00}, // o
{0xfc,0x24,0x24,0x24,0x18,0x00}, // p
{0x18,0x24,0x24,0x24,0xfc,0x80}, // q
{0x3c,0x04,0x02,0x02,0x00,0x00}, // r
{0x24,0x2c,0x2a,0x2a,0x10,0x00}, // s
{0x02,0x1f,0x22,0x20,0x00,0x00}, // t
{0x1e,0x20,0x20,0x20,0x1e,0x00}, // u
{0x06,0x18,0x20,0x18,0x06,0x00}, // v
{0x1e,0x30,0x1c,0x30,0x0e,0x00}, // w
{0x22,0x14,0x08,0x14,0x22,0x00}, // x
{0x0c,0x10,0xa0,0xa0,0x7c,0x00}, // y
{0x22,0x32,0x2a,0x26,0x22,0x22}, // z
{0x0c,0x3f,0x21,0x00,0x00,0x00}, // {
{0x3f,0x00,0x00,0x00,0x00,0x00}, // |
{0x21,0x3f,0x0c,0x00,0x00,0x00}, // }
{0x02,0x01,0x02,0x01,0x00,0x00}, // ~
{0x00,0x00,0x00,0x00,0x00,0x00}
};

View file

@ -1,27 +1,33 @@
#ifndef __ili9341_H #ifndef __ili9341_H
#define __ili9341_H #define __ili9341_H
#include "singleton.h" #include <f4ll_cpp/singleton.h>
#include <f4ll_cpp/dmahelper.h>
#include <inttypes.h> #include <inttypes.h>
#include <initializer_list> #include <initializer_list>
#include "main.h" #include "main.h"
class Ili9341Fsmc : public Singleton<Ili9341Fsmc> class Ili9341Fsmc : public Singleton<Ili9341Fsmc>, private DmaHelper
{ {
public: public:
Ili9341Fsmc(volatile uint16_t *reg, volatile uint16_t *ram, Ili9341Fsmc(volatile uint16_t *reg, volatile uint16_t *ram,
DMA_TypeDef *dma, uint32_t dmaStream, DMA_TypeDef *dma, uint32_t dmaStream,
bool horizontal = true); bool horizontal = true);
void FillRect(uint16_t color); void FillRect(uint16_t color, bool async = true);
void FillRect(uint16_t x, uint16_t y, uint16_t width, uint16_t height, uint16_t color); void FillRect(uint16_t x, uint16_t y, uint16_t width, uint16_t height, uint16_t color, bool async = true);
uint16_t Width() { return m_width; } uint16_t Width() { return m_width; }
uint16_t Height() { return m_height; } uint16_t Height() { return m_height; }
void SetCursor(uint16_t x, uint16_t y, uint16_t fgColor, uint16_t bgColor);
void PrintChar(char c, uint16_t x, uint16_t y, uint16_t fgColor, uint16_t bgColor);
void PrintChar(char c);
void Print(char const *str, uint8_t len = 0);
inline void WaitDmaIddle() { while(m_dmaEngineBusy); } inline void WaitDmaIdle() { while(m_dmaEngineBusy); }
void Test(); void Test();
static void HandleDmaIrq(Ili9341Fsmc *obj) { obj->HandleDmaIrq(); }
private: private:
inline void WriteCmd(uint16_t cmd) { *m_reg = cmd; } inline void WriteCmd(uint16_t cmd) { *m_reg = cmd; }
@ -33,12 +39,9 @@ private:
volatile uint16_t * const m_reg; volatile uint16_t * const m_reg;
volatile uint16_t * const m_ram; volatile uint16_t * const m_ram;
DMA_TypeDef *m_dma; void HandleDmaIrq();
uint32_t m_dmaStream;
friend void HandleLcdDmaIrq();
void SetupDmaSize(uint32_t size); void SetupDmaSize(uint32_t size);
void DmaTransferComplete(); volatile bool m_dmaEngineBusy = false;
bool m_dmaEngineBusy = false;
uint32_t m_dmaRemainingPixels = 0; uint32_t m_dmaRemainingPixels = 0;
uint16_t m_dmaColor = 0; uint16_t m_dmaColor = 0;
@ -50,6 +53,11 @@ private:
uint16_t m_rectWidth; uint16_t m_rectWidth;
uint16_t m_rectHeight; uint16_t m_rectHeight;
uint16_t m_xPos = 0;
uint16_t m_yPos = 0;
uint16_t m_fgColor = ILI9341_WHITE;
uint16_t m_bgColor = ILI9341_BLACK;
enum Commands { enum Commands {
ILI9341_NOP = 0x00, ILI9341_NOP = 0x00,
ILI9341_RESET = 0x01, ILI9341_RESET = 0x01,
@ -130,6 +138,11 @@ private:
ILI9341_PRC = 0xF7, ILI9341_PRC = 0xF7,
}; };
static const uint8_t CHRHEIGHT = 8;
static const uint8_t CHRWIDTH = 6;
static const uint8_t CHRCOUNT = 96;
static const uint8_t m_font[CHRCOUNT][CHRWIDTH];
public: public:
enum Colors { enum Colors {
ILI9341_BLACK = 0x0000, /* 0, 0, 0 */ ILI9341_BLACK = 0x0000, /* 0, 0, 0 */

View file

@ -12,10 +12,23 @@
void HandleLcdDmaIrq() void HandleLcdDmaIrq()
{ {
// DMA2 Stream4 // DMA2 Stream4
if(LL_DMA_IsActiveFlag_TC4(DMA2)) { Ili9341Fsmc::HandleDmaIrq(&Ili9341Fsmc::Instance());
LL_DMA_DisableStream(DMA2, LL_DMA_STREAM_4); }
LL_DMA_ClearFlag_TC4(DMA2);
Ili9341Fsmc::Instance().DmaTransferComplete(); void HandleConsoleRxDmaIrq()
} else if(LL_DMA_IsActiveFlag_TE4(DMA2)) {
LL_DMA_ClearFlag_TE4(DMA2); if(g_console)
g_console->HandleRxDmaIrq();
}
void HandleConsoleTxDmaIrq()
{
if(g_console)
g_console->HandleTxDmaIrq();
}
void HandleConsoleUsartIrq()
{
if(g_console)
g_console->HandleUsartIrq();
} }

View file

@ -15,6 +15,10 @@ extern "C" {
void HandleLcdDmaIrq(); void HandleLcdDmaIrq();
void HandleConsoleRxDmaIrq();
void HandleConsoleTxDmaIrq();
void HandleConsoleUsartIrq();
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

View file

@ -1,55 +0,0 @@
/*
* mainloop.cpp
*
* Created on: Sep 11, 2019
* Author: abody
*/
#include <ili9341.h>
#include "main.h"
#include <mainloop.h>
#include <initializer_list>
#define BORDER 60
#define BARWIDTH 2
void MainLoop()
{
uint16_t colors[] = {
Ili9341Fsmc::ILI9341_RED, Ili9341Fsmc::ILI9341_ORANGE, Ili9341Fsmc::ILI9341_YELLOW, Ili9341Fsmc::ILI9341_GREENYELLOW,
Ili9341Fsmc::ILI9341_GREEN, Ili9341Fsmc::ILI9341_CYAN, Ili9341Fsmc::ILI9341_BLUE, Ili9341Fsmc::ILI9341_MAGENTA
};
static uint16_t const colorCount = sizeof(colors)/sizeof(colors[0]);
uint32_t lastTick = 0;
uint32_t tmpTick;
uint32_t lastDiff;
//LL_SYSTICK_EnableIT();
Ili9341Fsmc &lcd(Ili9341Fsmc::Init(nullptr, nullptr, DMA2, LL_DMA_STREAM_4, true));
lcd.FillRect(Ili9341Fsmc::ILI9341_WHITE);
lcd.FillRect(BORDER, BORDER, lcd.Width()- BORDER * 2, lcd.Height()-BORDER * 2, Ili9341Fsmc::ILI9341_BLACK);
uint16_t offset = 0;
uint16_t maxidx = (lcd.Width() - BARWIDTH) / BARWIDTH;
for(;;) {
uint16_t idx = 0;
while(idx <= maxidx ) {
lcd.FillRect(idx * BARWIDTH, 0, BARWIDTH, lcd.Height(), colors[(idx+offset) % colorCount]);
++idx;
}
offset = (offset+1)%colorCount;
tmpTick = HAL_GetTick();
lastDiff = tmpTick - lastTick;
do tmpTick = HAL_GetTick(); while(tmpTick - lastTick < 20);
lastTick = tmpTick;
// LL_GPIO_TogglePin(LED1_GPIO_Port, LED1_Pin);
// LL_GPIO_TogglePin(LED2_GPIO_Port, LED2_Pin);
// LL_mDelay(25);
}
}
MainLoop::MainLoop()
{
}

View file

@ -1,27 +0,0 @@
/*
* mainloop.h
*
* Created on: Sep 11, 2019
* Author: abody
*/
#ifndef MAINLOOP_H_
#define MAINLOOP_H_
#if defined(__cplusplus)
extern "C" {
#endif
void MainLoop();
#if defined(__cplusplus)
class MainLoop {
MainLoop();
};
#endif // __cplusplus
#if defined(__cplusplus)
}
#endif
#endif /* MAINLOOP_H_ */

View file

@ -13576,7 +13576,7 @@ typedef struct
#define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */ #define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
#define ETH_DMASR_TPS_Suspended_Pos (21U) #define ETH_DMASR_TPS_Suspended_Pos (21U)
#define ETH_DMASR_TPS_Suspended_Msk (0x3UL << ETH_DMASR_TPS_Suspended_Pos) /*!< 0x00600000 */ #define ETH_DMASR_TPS_Suspended_Msk (0x3UL << ETH_DMASR_TPS_Suspended_Pos) /*!< 0x00600000 */
#define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailabe */ #define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailable */
#define ETH_DMASR_TPS_Closing_Pos (20U) #define ETH_DMASR_TPS_Closing_Pos (20U)
#define ETH_DMASR_TPS_Closing_Msk (0x7UL << ETH_DMASR_TPS_Closing_Pos) /*!< 0x00700000 */ #define ETH_DMASR_TPS_Closing_Msk (0x7UL << ETH_DMASR_TPS_Closing_Pos) /*!< 0x00700000 */
#define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */ #define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
@ -13598,7 +13598,7 @@ typedef struct
#define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */ #define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
#define ETH_DMASR_RPS_Queuing_Pos (17U) #define ETH_DMASR_RPS_Queuing_Pos (17U)
#define ETH_DMASR_RPS_Queuing_Msk (0x7UL << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */ #define ETH_DMASR_RPS_Queuing_Msk (0x7UL << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */
#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */ #define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */
#define ETH_DMASR_NIS_Pos (16U) #define ETH_DMASR_NIS_Pos (16U)
#define ETH_DMASR_NIS_Msk (0x1UL << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */ #define ETH_DMASR_NIS_Msk (0x1UL << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */
#define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */ #define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
@ -15295,10 +15295,6 @@ typedef struct
((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM8) || \
((INSTANCE) == TIM9) || \ ((INSTANCE) == TIM9) || \
((INSTANCE) == TIM12)) ((INSTANCE) == TIM12))
/****************** TIM Instances : supporting synchronization ****************/
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
/********************** TIM Instances : 32 bit Counter ************************/ /********************** TIM Instances : 32 bit Counter ************************/
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \ #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
((INSTANCE) == TIM5)) ((INSTANCE) == TIM5))

View file

@ -122,11 +122,11 @@
#endif /* USE_HAL_DRIVER */ #endif /* USE_HAL_DRIVER */
/** /**
* @brief CMSIS version number V2.6.3 * @brief CMSIS version number V2.6.4
*/ */
#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */ #define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */ #define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */ #define __STM32F4xx_CMSIS_VERSION_SUB2 (0x04U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\ #define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\ |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\

View file

@ -7,7 +7,7 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics. * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.</center></h2>
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software component is licensed by ST under BSD 3-Clause license,
@ -236,6 +236,16 @@
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
#if defined(STM32G4) || defined(STM32H7)
#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
#endif
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32H7) || defined(STM32F4)
#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
#endif
/** /**
* @} * @}
*/ */
@ -296,8 +306,17 @@
#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI
#endif
#endif /* STM32L4 */ #endif /* STM32L4 */
#if defined(STM32G0)
#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1
#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2
#endif
#if defined(STM32H7) #if defined(STM32H7)
#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
@ -355,6 +374,9 @@
#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT #define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT #define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT
#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
#endif /* STM32H7 */ #endif /* STM32H7 */
/** /**
@ -450,7 +472,9 @@
#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 #define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 #define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 #define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
#endif #define FLASH_FLAG_WDW FLASH_FLAG_WBNE
#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
#endif /* STM32H7 */
/** /**
* @} * @}
@ -486,6 +510,13 @@
#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 #define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 #define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 #define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
#if defined(STM32G4)
#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster
#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster
#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD
#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
#endif /* STM32G4 */
/** /**
* @} * @}
*/ */
@ -494,7 +525,7 @@
/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
* @{ * @{
*/ */
#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) #if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
@ -547,18 +578,25 @@
#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 #define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2
#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 #define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2
#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 #define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2
#endif
#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \
defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx)
#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS
#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS
#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS
#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
#endif /* STM32H7 */
#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32H7) #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7)
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32H7*/ #endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/
#if defined(STM32L1) #if defined(STM32L1)
#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
@ -599,6 +637,185 @@
#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER #define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
#if defined(STM32G4)
#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig
#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable
#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable
#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset
#endif /* STM32G4 */
#if defined(STM32H7)
#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
#endif /* STM32H7 */
#if defined(STM32F3)
/** @brief Constants defining available sources associated to external events.
*/
#define HRTIM_EVENTSRC_1 (0x00000000U)
#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0)
#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1)
#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
/** @brief Constants defining the events that can be selected to configure the
* set/reset crossbar of a timer output
*/
#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1)
#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2)
#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3)
#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4)
#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5)
#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6)
#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7)
#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8)
#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9)
#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1)
#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2)
#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3)
#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4)
#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5)
#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6)
#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7)
#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8)
#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9)
/** @brief Constants defining the event filtering applied to external events
* by a timer
*/
#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U)
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1)
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)
#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
/** @brief Constants defining the DLL calibration periods (in micro seconds)
*/
#define HRTIM_CALIBRATIONRATE_7300 0x00000000U
#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0)
#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1)
#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
#endif /* STM32F3 */
/** /**
* @} * @}
*/ */
@ -738,6 +955,12 @@
#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
#if defined(STM32L1) || defined(STM32L4) || defined(STM32H7)
#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
#endif
/** /**
* @} * @}
*/ */
@ -753,7 +976,6 @@
#define I2S_FLAG_TXE I2S_FLAG_TXP #define I2S_FLAG_TXE I2S_FLAG_TXP
#define I2S_FLAG_RXNE I2S_FLAG_RXP #define I2S_FLAG_RXNE I2S_FLAG_RXP
#define I2S_FLAG_FRE I2S_FLAG_TIFRE
#endif #endif
#if defined(STM32F7) #if defined(STM32F7)
@ -824,6 +1046,16 @@
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
#if defined(STM32H7)
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL
#endif /* STM32H7 */
/** /**
* @} * @}
*/ */
@ -971,6 +1203,24 @@
#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE #define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
#endif #endif
#if defined(STM32H7)
#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1
#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2
#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1
#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2
#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1
#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2
#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1
#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1
#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2
#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1
#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2
#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2
#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1
#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2
#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
#endif
/** /**
* @} * @}
*/ */
@ -1199,6 +1449,30 @@
#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
#if defined(STM32L4) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt
#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End
#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT
#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT
#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt
#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End
#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT
#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT
#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt
#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End
#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT
#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT
#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt
#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End
#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT
#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT
#endif /* STM32L4 || STM32F4 || STM32F7 || STM32H7 */
/** /**
* @} * @}
*/ */
@ -1221,6 +1495,13 @@
#endif #endif
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode
#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode
#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */
/** /**
* @} * @}
*/ */
@ -1250,16 +1531,18 @@
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) #if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32G4)
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT #define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT #define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT #define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32G4 */
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32G4)
#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA #define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA #define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA #define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA #define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 */ #endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32G4 */
#if defined(STM32F4) #if defined(STM32F4)
#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT #define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT
@ -1278,6 +1561,13 @@
/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
* @{ * @{
*/ */
#if defined(STM32G0)
#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD
#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD
#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD
#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler
#endif
#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown #define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
@ -1350,14 +1640,14 @@
#define HAL_TIM_DMAError TIM_DMAError #define HAL_TIM_DMAError TIM_DMAError
#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
#if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0) #if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro #define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT #define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback #define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent #define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent
#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT #define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT
#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA #define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA
#endif /* STM32H7 || STM32G0 || STM32F7 || STM32F4 || STM32L0 */ #endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */
/** /**
* @} * @}
*/ */
@ -2476,12 +2766,28 @@
#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE #define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE #define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET #define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
#if defined(STM32H7)
#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE
#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE
#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE
#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE
#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/
#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/
#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED
#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED
#endif
#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE #define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE #define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE #define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET #define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET #define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE #define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE #define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET #define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
@ -2814,6 +3120,15 @@
#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED #define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED #define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
#if defined(STM32L1)
#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
#endif /* STM32L1 */
#if defined(STM32F4) #if defined(STM32F4)
#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET #define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET #define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
@ -2930,7 +3245,7 @@
#if defined(STM32L4) #if defined(STM32L4)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
#elif defined(STM32WB) || defined(STM32G0) #elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4)
#else #else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
#endif #endif
@ -3058,7 +3373,7 @@
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{ * @{
*/ */
#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) #if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32G4)
#else #else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif #endif
@ -3174,7 +3489,7 @@
#define SDIO_IRQHandler SDMMC1_IRQHandler #define SDIO_IRQHandler SDMMC1_IRQHandler
#endif #endif
#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) #if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7)
#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef #define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef
#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef #define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef
#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef #define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
@ -3421,13 +3736,23 @@
/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose /** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose
* @{ * @{
*/ */
#if defined (STM32H7) || defined (STM32F3) #if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)
#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT #define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA #define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart #define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT #define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA #define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop #define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
#endif
/**
* @}
*/
/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
* @{
*/
#if defined (STM32L4)
#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
#endif #endif
/** /**
* @} * @}

View file

@ -197,6 +197,18 @@ typedef enum
* @} * @}
*/ */
/* Exported variables --------------------------------------------------------*/
/** @addtogroup HAL_Exported_Variables
* @{
*/
extern __IO uint32_t uwTick;
extern uint32_t uwTickPrio;
extern HAL_TickFreqTypeDef uwTickFreq;
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/
/** @addtogroup HAL_Exported_Functions /** @addtogroup HAL_Exported_Functions
* @{ * @{

View file

@ -0,0 +1,184 @@
/**
******************************************************************************
* @file stm32f4xx_hal_crc.h
* @author MCD Application Team
* @brief Header file of CRC HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F4xx_HAL_CRC_H
#define STM32F4xx_HAL_CRC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
/** @addtogroup CRC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup CRC_Exported_Types CRC Exported Types
* @{
*/
/**
* @brief CRC HAL State Structure definition
*/
typedef enum
{
HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */
HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */
HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */
HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */
HAL_CRC_STATE_ERROR = 0x04U /*!< CRC error state */
} HAL_CRC_StateTypeDef;
/**
* @brief CRC Handle Structure definition
*/
typedef struct
{
CRC_TypeDef *Instance; /*!< Register base address */
HAL_LockTypeDef Lock; /*!< CRC Locking object */
__IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */
} CRC_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CRC_Exported_Constants CRC Exported Constants
* @{
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup CRC_Exported_Macros CRC Exported Macros
* @{
*/
/** @brief Reset CRC handle state.
* @param __HANDLE__ CRC handle.
* @retval None
*/
#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
/**
* @brief Reset CRC Data Register.
* @param __HANDLE__ CRC handle
* @retval None
*/
#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
/**
* @brief Store data in the Independent Data (ID) register.
* @param __HANDLE__ CRC handle
* @param __VALUE__ Value to be stored in the ID register
* @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits
* @retval None
*/
#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
/**
* @brief Return the data stored in the Independent Data (ID) register.
* @param __HANDLE__ CRC handle
* @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits
* @retval Value of the ID register
*/
#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
/**
* @}
*/
/* Private macros --------------------------------------------------------*/
/** @defgroup CRC_Private_Macros CRC Private Macros
* @{
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CRC_Exported_Functions CRC Exported Functions
* @{
*/
/* Initialization and de-initialization functions ****************************/
/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc);
void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
/**
* @}
*/
/* Peripheral Control functions ***********************************************/
/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
* @{
*/
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
/**
* @}
*/
/* Peripheral State and Error functions ***************************************/
/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
* @{
*/
HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F4xx_HAL_CRC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

View file

@ -44,9 +44,7 @@ extern "C" {
*/ */
typedef enum typedef enum
{ {
HAL_EXTI_COMMON_CB_ID = 0x00U, HAL_EXTI_COMMON_CB_ID = 0x00U
HAL_EXTI_RISING_CB_ID = 0x01U,
HAL_EXTI_FALLING_CB_ID = 0x02U,
} EXTI_CallbackIDTypeDef; } EXTI_CallbackIDTypeDef;
/** /**
@ -55,8 +53,7 @@ typedef enum
typedef struct typedef struct
{ {
uint32_t Line; /*!< Exti line number */ uint32_t Line; /*!< Exti line number */
void (* RisingCallback)(void); /*!< Exti rising callback */ void (* PendingCallback)(void); /*!< Exti pending callback */
void (* FallingCallback)(void); /*!< Exti falling callback */
} EXTI_HandleTypeDef; } EXTI_HandleTypeDef;
/** /**
@ -70,6 +67,9 @@ typedef struct
This parameter can be a combination of @ref EXTI_Mode */ This parameter can be a combination of @ref EXTI_Mode */
uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
can be a value of @ref EXTI_Trigger */ can be a value of @ref EXTI_Trigger */
uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured.
This parameter is only possible for line 0 to 15. It
can be a value of @ref EXTI_GPIOSel */
} EXTI_ConfigTypeDef; } EXTI_ConfigTypeDef;
/** /**
@ -84,29 +84,44 @@ typedef struct
/** @defgroup EXTI_Line EXTI Line /** @defgroup EXTI_Line EXTI Line
* @{ * @{
*/ */
#define EXTI_LINE_0 EXTI_IMR_IM0 /*!< External interrupt line 0 */ #define EXTI_LINE_0 (EXTI_GPIO | 0x00u) /*!< External interrupt line 0 */
#define EXTI_LINE_1 EXTI_IMR_IM1 /*!< External interrupt line 1 */ #define EXTI_LINE_1 (EXTI_GPIO | 0x01u) /*!< External interrupt line 1 */
#define EXTI_LINE_2 EXTI_IMR_IM2 /*!< External interrupt line 2 */ #define EXTI_LINE_2 (EXTI_GPIO | 0x02u) /*!< External interrupt line 2 */
#define EXTI_LINE_3 EXTI_IMR_IM3 /*!< External interrupt line 3 */ #define EXTI_LINE_3 (EXTI_GPIO | 0x03u) /*!< External interrupt line 3 */
#define EXTI_LINE_4 EXTI_IMR_IM4 /*!< External interrupt line 4 */ #define EXTI_LINE_4 (EXTI_GPIO | 0x04u) /*!< External interrupt line 4 */
#define EXTI_LINE_5 EXTI_IMR_IM5 /*!< External interrupt line 5 */ #define EXTI_LINE_5 (EXTI_GPIO | 0x05u) /*!< External interrupt line 5 */
#define EXTI_LINE_6 EXTI_IMR_IM6 /*!< External interrupt line 6 */ #define EXTI_LINE_6 (EXTI_GPIO | 0x06u) /*!< External interrupt line 6 */
#define EXTI_LINE_7 EXTI_IMR_IM7 /*!< External interrupt line 7 */ #define EXTI_LINE_7 (EXTI_GPIO | 0x07u) /*!< External interrupt line 7 */
#define EXTI_LINE_8 EXTI_IMR_IM8 /*!< External interrupt line 8 */ #define EXTI_LINE_8 (EXTI_GPIO | 0x08u) /*!< External interrupt line 8 */
#define EXTI_LINE_9 EXTI_IMR_IM9 /*!< External interrupt line 9 */ #define EXTI_LINE_9 (EXTI_GPIO | 0x09u) /*!< External interrupt line 9 */
#define EXTI_LINE_10 EXTI_IMR_IM10 /*!< External interrupt line 10 */ #define EXTI_LINE_10 (EXTI_GPIO | 0x0Au) /*!< External interrupt line 10 */
#define EXTI_LINE_11 EXTI_IMR_IM11 /*!< External interrupt line 11 */ #define EXTI_LINE_11 (EXTI_GPIO | 0x0Bu) /*!< External interrupt line 11 */
#define EXTI_LINE_12 EXTI_IMR_IM12 /*!< External interrupt line 12 */ #define EXTI_LINE_12 (EXTI_GPIO | 0x0Cu) /*!< External interrupt line 12 */
#define EXTI_LINE_13 EXTI_IMR_IM13 /*!< External interrupt line 13 */ #define EXTI_LINE_13 (EXTI_GPIO | 0x0Du) /*!< External interrupt line 13 */
#define EXTI_LINE_14 EXTI_IMR_IM14 /*!< External interrupt line 14 */ #define EXTI_LINE_14 (EXTI_GPIO | 0x0Eu) /*!< External interrupt line 14 */
#define EXTI_LINE_15 EXTI_IMR_IM15 /*!< External interrupt line 15 */ #define EXTI_LINE_15 (EXTI_GPIO | 0x0Fu) /*!< External interrupt line 15 */
#define EXTI_LINE_16 EXTI_IMR_IM16 /*!< External interrupt line 16 Connected to the PVD Output */ #define EXTI_LINE_16 (EXTI_CONFIG | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */
#define EXTI_LINE_17 EXTI_IMR_IM17 /*!< External interrupt line 17 Connected to the RTC Alarm event */ #define EXTI_LINE_17 (EXTI_CONFIG | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */
#define EXTI_LINE_18 EXTI_IMR_IM18 /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */ #if defined(EXTI_IMR_IM18)
#define EXTI_LINE_19 EXTI_IMR_IM19 /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ #define EXTI_LINE_18 (EXTI_CONFIG | 0x12u) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */
#define EXTI_LINE_20 EXTI_IMR_IM20 /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */ #else
#define EXTI_LINE_21 EXTI_IMR_IM21 /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */ #define EXTI_LINE_18 (EXTI_RESERVED | 0x12u) /*!< No interrupt supported in this line */
#define EXTI_LINE_22 EXTI_IMR_IM22 /*!< External interrupt line 22 Connected to the RTC Wakeup event */ #endif /* EXTI_IMR_IM18 */
#if defined(EXTI_IMR_IM19)
#define EXTI_LINE_19 (EXTI_CONFIG | 0x13u) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
#else
#define EXTI_LINE_19 (EXTI_RESERVED | 0x13u) /*!< No interrupt supported in this line */
#endif /* EXTI_IMR_IM19 */
#if defined(EXTI_IMR_IM20)
#define EXTI_LINE_20 (EXTI_CONFIG | 0x14u) /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */
#else
#define EXTI_LINE_20 (EXTI_RESERVED | 0x14u) /*!< No interrupt supported in this line */
#endif /* EXTI_IMR_IM20 */
#define EXTI_LINE_21 (EXTI_CONFIG | 0x15u) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
#define EXTI_LINE_22 (EXTI_CONFIG | 0x16u) /*!< External interrupt line 22 Connected to the RTC Wakeup event */
#if defined(EXTI_IMR_IM23)
#define EXTI_LINE_23 (EXTI_CONFIG | 0x17u) /*!< External interrupt line 23 Connected to the LPTIM1 asynchronous event */
#endif /* EXTI_IMR_IM23 */
/** /**
* @} * @}
@ -115,8 +130,9 @@ typedef struct
/** @defgroup EXTI_Mode EXTI Mode /** @defgroup EXTI_Mode EXTI Mode
* @{ * @{
*/ */
#define EXTI_MODE_INTERRUPT 0x00000000U #define EXTI_MODE_NONE 0x00000000u
#define EXTI_MODE_EVENT 0x00000004U #define EXTI_MODE_INTERRUPT 0x00000001u
#define EXTI_MODE_EVENT 0x00000002u
/** /**
* @} * @}
*/ */
@ -125,9 +141,46 @@ typedef struct
* @{ * @{
*/ */
#define EXTI_TRIGGER_RISING 0x00000008U #define EXTI_TRIGGER_NONE 0x00000000u
#define EXTI_TRIGGER_FALLING 0x0000000CU #define EXTI_TRIGGER_RISING 0x00000001u
#define EXTI_TRIGGER_RISING_FALLING 0x00000010U #define EXTI_TRIGGER_FALLING 0x00000002u
#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
/**
* @}
*/
/** @defgroup EXTI_GPIOSel EXTI GPIOSel
* @brief
* @{
*/
#define EXTI_GPIOA 0x00000000u
#define EXTI_GPIOB 0x00000001u
#define EXTI_GPIOC 0x00000002u
#if defined (GPIOD)
#define EXTI_GPIOD 0x00000003u
#endif /* GPIOD */
#if defined (GPIOE)
#define EXTI_GPIOE 0x00000004u
#endif /* GPIOE */
#if defined (GPIOF)
#define EXTI_GPIOF 0x00000005u
#endif /* GPIOF */
#if defined (GPIOG)
#define EXTI_GPIOG 0x00000006u
#endif /* GPIOG */
#if defined (GPIOH)
#define EXTI_GPIOH 0x00000007u
#endif /* GPIOH */
#if defined (GPIOI)
#define EXTI_GPIOI 0x00000008u
#endif /* GPIOI */
#if defined (GPIOJ)
#define EXTI_GPIOJ 0x00000009u
#endif /* GPIOJ */
#if defined (GPIOK)
#define EXTI_GPIOK 0x0000000Au
#endif /* GPIOK */
/** /**
* @} * @}
*/ */
@ -149,6 +202,20 @@ typedef struct
/** @defgroup EXTI_Private_Constants EXTI Private Constants /** @defgroup EXTI_Private_Constants EXTI Private Constants
* @{ * @{
*/ */
/**
* @brief EXTI Line property definition
*/
#define EXTI_PROPERTY_SHIFT 24u
#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)
#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT)
#define EXTI_PROPERTY_MASK (EXTI_CONFIG | EXTI_GPIO)
/**
* @brief EXTI bit usage
*/
#define EXTI_PIN_MASK 0x0000001Fu
/** /**
* @brief EXTI Mask for interrupt & event mode * @brief EXTI Mask for interrupt & event mode
*/ */
@ -157,12 +224,16 @@ typedef struct
/** /**
* @brief EXTI Mask for trigger possibilities * @brief EXTI Mask for trigger possibilities
*/ */
#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING | EXTI_TRIGGER_RISING_FALLING) #define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
/** /**
* @brief EXTI Line number * @brief EXTI Line number
*/ */
#if defined(EXTI_IMR_IM23)
#define EXTI_LINE_NB 24UL
#else
#define EXTI_LINE_NB 23UL #define EXTI_LINE_NB 23UL
#endif /* EXTI_IMR_IM23 */
/** /**
* @} * @}
@ -172,38 +243,73 @@ typedef struct
/** @defgroup EXTI_Private_Macros EXTI Private Macros /** @defgroup EXTI_Private_Macros EXTI Private Macros
* @{ * @{
*/ */
#define IS_EXTI_LINE(__LINE__) (((__LINE__) == EXTI_LINE_0) || \ #define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \
((__LINE__) == EXTI_LINE_1) || \ ((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
((__LINE__) == EXTI_LINE_2) || \ (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
((__LINE__) == EXTI_LINE_3) || \ (((__LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB))
((__LINE__) == EXTI_LINE_4) || \
((__LINE__) == EXTI_LINE_5) || \
((__LINE__) == EXTI_LINE_6) || \
((__LINE__) == EXTI_LINE_7) || \
((__LINE__) == EXTI_LINE_8) || \
((__LINE__) == EXTI_LINE_9) || \
((__LINE__) == EXTI_LINE_10) || \
((__LINE__) == EXTI_LINE_11) || \
((__LINE__) == EXTI_LINE_12) || \
((__LINE__) == EXTI_LINE_13) || \
((__LINE__) == EXTI_LINE_14) || \
((__LINE__) == EXTI_LINE_15) || \
((__LINE__) == EXTI_LINE_16) || \
((__LINE__) == EXTI_LINE_17) || \
((__LINE__) == EXTI_LINE_18) || \
((__LINE__) == EXTI_LINE_19) || \
((__LINE__) == EXTI_LINE_20) || \
((__LINE__) == EXTI_LINE_21) || \
((__LINE__) == EXTI_LINE_22))
#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & ~EXTI_MODE_MASK) == 0x00U)) #define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \
(((__LINE__) & ~EXTI_MODE_MASK) == 0x00u))
#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00U) #define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
#define IS_EXTI_PENDING_EDGE(__LINE__) (((__LINE__) == EXTI_TRIGGER_FALLING) || \ #define IS_EXTI_PENDING_EDGE(__LINE__) (((__LINE__) == EXTI_TRIGGER_FALLING) || \
((__LINE__) == EXTI_TRIGGER_RISING) || \ ((__LINE__) == EXTI_TRIGGER_RISING) || \
((__LINE__) == EXTI_TRIGGER_RISING_FALLING)) ((__LINE__) == EXTI_TRIGGER_RISING_FALLING))
#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u)
#if !defined (GPIOD)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOH))
#elif !defined (GPIOE)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOD) || \
((__PORT__) == EXTI_GPIOH))
#elif !defined (GPIOF)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOD) || \
((__PORT__) == EXTI_GPIOE) || \
((__PORT__) == EXTI_GPIOH))
#elif !defined (GPIOI)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOD) || \
((__PORT__) == EXTI_GPIOE) || \
((__PORT__) == EXTI_GPIOF) || \
((__PORT__) == EXTI_GPIOG) || \
((__PORT__) == EXTI_GPIOH))
#elif !defined (GPIOJ)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOD) || \
((__PORT__) == EXTI_GPIOE) || \
((__PORT__) == EXTI_GPIOF) || \
((__PORT__) == EXTI_GPIOG) || \
((__PORT__) == EXTI_GPIOH) || \
((__PORT__) == EXTI_GPIOI))
#else
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOD) || \
((__PORT__) == EXTI_GPIOE) || \
((__PORT__) == EXTI_GPIOF) || \
((__PORT__) == EXTI_GPIOG) || \
((__PORT__) == EXTI_GPIOH) || \
((__PORT__) == EXTI_GPIOI) || \
((__PORT__) == EXTI_GPIOJ) || \
((__PORT__) == EXTI_GPIOK))
#endif /* GPIOD */
#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16U) #define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16U)
/** /**
* @} * @}

View file

@ -262,7 +262,7 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
* @{ * @{
*/ */
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) #define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define IS_GPIO_PIN(PIN) ((((PIN) & GPIO_PIN_MASK ) != 0x00U) && (((PIN) & ~GPIO_PIN_MASK) == 0x00U)) #define IS_GPIO_PIN(PIN) (((((uint32_t)PIN) & GPIO_PIN_MASK ) != 0x00U) && ((((uint32_t)PIN) & ~GPIO_PIN_MASK) == 0x00U))
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\ #define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
((MODE) == GPIO_MODE_OUTPUT_PP) ||\ ((MODE) == GPIO_MODE_OUTPUT_PP) ||\
((MODE) == GPIO_MODE_OUTPUT_OD) ||\ ((MODE) == GPIO_MODE_OUTPUT_OD) ||\

View file

@ -167,7 +167,7 @@ typedef struct
This parameter can be a value of @ref TIM_Encoder_Mode */ This parameter can be a value of @ref TIM_Encoder_Mode */
uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Input_Capture_Polarity */ This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
uint32_t IC1Selection; /*!< Specifies the input. uint32_t IC1Selection; /*!< Specifies the input.
This parameter can be a value of @ref TIM_Input_Capture_Selection */ This parameter can be a value of @ref TIM_Input_Capture_Selection */
@ -179,7 +179,7 @@ typedef struct
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Input_Capture_Polarity */ This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
uint32_t IC2Selection; /*!< Specifies the input. uint32_t IC2Selection; /*!< Specifies the input.
This parameter can be a value of @ref TIM_Input_Capture_Selection */ This parameter can be a value of @ref TIM_Input_Capture_Selection */
@ -231,7 +231,12 @@ typedef struct
uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
This parameter can be a value of @ref TIM_Master_Mode_Selection */ This parameter can be a value of @ref TIM_Master_Mode_Selection */
uint32_t MasterSlaveMode; /*!< Master/slave mode selection uint32_t MasterSlaveMode; /*!< Master/slave mode selection
This parameter can be a value of @ref TIM_Master_Slave_Mode */ This parameter can be a value of @ref TIM_Master_Slave_Mode
@note When the Master/slave mode is enabled, the effect of
an event on the trigger input (TRGI) is delayed to allow a
perfect synchronization between the current timer and its
slaves (through TRGO). It is not mandatory in case of timer
synchronization mode. */
} TIM_MasterConfigTypeDef; } TIM_MasterConfigTypeDef;
/** /**
@ -588,6 +593,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
* @} * @}
*/ */
/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
* @{
*/
#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */
#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */
/**
* @}
*/
/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
* @{ * @{
*/ */
@ -1020,15 +1034,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
* @retval None * @retval None
*/ */
#define __HAL_TIM_DISABLE(__HANDLE__) \ #define __HAL_TIM_DISABLE(__HANDLE__) \
do { \ do { \
if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
{ \ { \
if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
{ \ { \
(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
} \ } \
} \ } \
} while(0) } while(0)
/** /**
* @brief Disable the TIM main Output. * @brief Disable the TIM main Output.
@ -1037,15 +1051,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
* @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
*/ */
#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
do { \ do { \
if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
{ \ { \
if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
{ \ { \
(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
} \ } \
} \ } \
} while(0) } while(0)
/** /**
* @brief Disable the TIM main Output. * @brief Disable the TIM main Output.
@ -1172,7 +1186,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
* @arg TIM_IT_BREAK: Break interrupt * @arg TIM_IT_BREAK: Break interrupt
* @retval The state of TIM_IT (SET or RESET). * @retval The state of TIM_IT (SET or RESET).
*/ */
#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
== (__INTERRUPT__)) ? SET : RESET)
/** @brief Clear the TIM interrupt pending bits. /** @brief Clear the TIM interrupt pending bits.
* @param __HANDLE__ TIM handle * @param __HANDLE__ TIM handle
@ -1220,8 +1235,7 @@ mode.
* @param __HANDLE__ TIM handle. * @param __HANDLE__ TIM handle.
* @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
*/ */
#define __HAL_TIM_GET_COUNTER(__HANDLE__) \ #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
((__HANDLE__)->Instance->CNT)
/** /**
* @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function.
@ -1230,18 +1244,17 @@ mode.
* @retval None * @retval None
*/ */
#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
do{ \ do{ \
(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
(__HANDLE__)->Init.Period = (__AUTORELOAD__); \ (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
} while(0) } while(0)
/** /**
* @brief Get the TIM Autoreload Register value on runtime. * @brief Get the TIM Autoreload Register value on runtime.
* @param __HANDLE__ TIM handle. * @param __HANDLE__ TIM handle.
* @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
*/ */
#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \ #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
((__HANDLE__)->Instance->ARR)
/** /**
* @brief Set the TIM Clock Division value on runtime without calling another time any Init function. * @brief Set the TIM Clock Division value on runtime without calling another time any Init function.
@ -1254,11 +1267,11 @@ mode.
* @retval None * @retval None
*/ */
#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
do{ \ do{ \
(__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \
(__HANDLE__)->Instance->CR1 |= (__CKD__); \ (__HANDLE__)->Instance->CR1 |= (__CKD__); \
(__HANDLE__)->Init.ClockDivision = (__CKD__); \ (__HANDLE__)->Init.ClockDivision = (__CKD__); \
} while(0) } while(0)
/** /**
* @brief Get the TIM Clock Division value on runtime. * @brief Get the TIM Clock Division value on runtime.
@ -1268,8 +1281,7 @@ mode.
* @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
* @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
*/ */
#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \ #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
/** /**
* @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function. * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
@ -1289,10 +1301,10 @@ mode.
* @retval None * @retval None
*/ */
#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
do{ \ do{ \
TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
} while(0) } while(0)
/** /**
* @brief Get the TIM Input Capture prescaler on runtime. * @brief Get the TIM Input Capture prescaler on runtime.
@ -1328,10 +1340,10 @@ mode.
* @retval None * @retval None
*/ */
#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
((__HANDLE__)->Instance->CCR4 = (__COMPARE__))) ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)))
/** /**
* @brief Get the TIM Capture Compare Register value on runtime. * @brief Get the TIM Capture Compare Register value on runtime.
@ -1345,10 +1357,10 @@ mode.
* @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
*/ */
#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
((__HANDLE__)->Instance->CCR4)) ((__HANDLE__)->Instance->CCR4))
/** /**
* @brief Set the TIM Output compare preload. * @brief Set the TIM Output compare preload.
@ -1362,10 +1374,10 @@ mode.
* @retval None * @retval None
*/ */
#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE)) ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
/** /**
* @brief Reset the TIM Output compare preload. * @brief Reset the TIM Output compare preload.
@ -1379,10 +1391,52 @@ mode.
* @retval None * @retval None
*/ */
#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE)) ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE))
/**
* @brief Enable fast mode for a given channel.
* @param __HANDLE__ TIM handle.
* @param __CHANNEL__ TIM Channels to be configured.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @note When fast mode is enabled an active edge on the trigger input acts
* like a compare match on CCx output. Delay to sample the trigger
* input and to activate CCx output is reduced to 3 clock cycles.
* @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
* @retval None
*/
#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE))
/**
* @brief Disable fast mode for a given channel.
* @param __HANDLE__ TIM handle.
* @param __CHANNEL__ TIM Channels to be configured.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @note When fast mode is disabled CCx output behaves normally depending
* on counter and CCRx values even when the trigger is ON. The minimum
* delay to activate CCx output when an active edge occurs on the
* trigger input is 5 clock cycles.
* @retval None
*/
#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE))
/** /**
* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.
@ -1392,8 +1446,7 @@ mode.
* enabled) * enabled)
* @retval None * @retval None
*/ */
#define __HAL_TIM_URS_ENABLE(__HANDLE__) \ #define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
/** /**
* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
@ -1406,8 +1459,7 @@ mode.
* _ Update generation through the slave mode controller * _ Update generation through the slave mode controller
* @retval None * @retval None
*/ */
#define __HAL_TIM_URS_DISABLE(__HANDLE__) \ #define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
/** /**
* @brief Set the TIM Capture x input polarity on runtime. * @brief Set the TIM Capture x input polarity on runtime.
@ -1425,10 +1477,10 @@ mode.
* @retval None * @retval None
*/ */
#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
do{ \ do{ \
TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
}while(0) }while(0)
/** /**
* @} * @}
@ -1504,6 +1556,9 @@ mode.
#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
((__STATE__) == TIM_OCNIDLESTATE_RESET)) ((__STATE__) == TIM_OCNIDLESTATE_RESET))
#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \
((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
@ -1681,28 +1736,28 @@ mode.
#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER)
#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC)) ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
/** /**
* @} * @}
@ -1840,7 +1895,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel
HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */ /* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length); HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
uint32_t *pData2, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/** /**
* @} * @}
@ -1864,17 +1920,19 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel); HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel); uint32_t OutputChannel, uint32_t InputChannel);
HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,
uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig); HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t *BurstBuffer, uint32_t BurstLength); uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t *BurstBuffer, uint32_t BurstLength); uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
@ -1900,7 +1958,8 @@ void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
/* Callbacks Register/UnRegister functions ***********************************/ /* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
pTIM_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
@ -1930,8 +1989,8 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
/* Private functions----------------------------------------------------------*/ /* Private functions----------------------------------------------------------*/
/** @defgroup TIM_Private_Functions TIM Private Functions /** @defgroup TIM_Private_Functions TIM Private Functions
* @{ * @{
*/ */
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
@ -1950,8 +2009,8 @@ void TIM_ResetCallback(TIM_HandleTypeDef *htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */
/* End of private functions --------------------------------------------------*/ /* End of private functions --------------------------------------------------*/
/** /**

View file

@ -202,9 +202,9 @@ typedef struct
*/ */
/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions /** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
* @brief Timer Hall Sensor functions * @brief Timer Hall Sensor functions
* @{ * @{
*/ */
/* Timer Hall Sensor functions **********************************************/ /* Timer Hall Sensor functions **********************************************/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig); HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
@ -226,9 +226,9 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
*/ */
/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions /** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
* @brief Timer Complementary Output Compare functions * @brief Timer Complementary Output Compare functions
* @{ * @{
*/ */
/* Timer Complementary Output Compare functions *****************************/ /* Timer Complementary Output Compare functions *****************************/
/* Blocking mode: Polling */ /* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
@ -246,9 +246,9 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann
*/ */
/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions /** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
* @brief Timer Complementary PWM functions * @brief Timer Complementary PWM functions
* @{ * @{
*/ */
/* Timer Complementary PWM functions ****************************************/ /* Timer Complementary PWM functions ****************************************/
/* Blocking mode: Polling */ /* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
@ -265,9 +265,9 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
*/ */
/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions /** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
* @brief Timer Complementary One Pulse functions * @brief Timer Complementary One Pulse functions
* @{ * @{
*/ */
/* Timer Complementary One Pulse functions **********************************/ /* Timer Complementary One Pulse functions **********************************/
/* Blocking mode: Polling */ /* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
@ -281,15 +281,20 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t
*/ */
/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions /** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
* @brief Peripheral Control functions * @brief Peripheral Control functions
* @{ * @{
*/ */
/* Extended Control functions ************************************************/ /* Extended Control functions ************************************************/
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig); uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
TIM_MasterConfigTypeDef *sMasterConfig);
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
/** /**
* @} * @}
@ -323,7 +328,7 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
/* End of exported functions -------------------------------------------------*/ /* End of exported functions -------------------------------------------------*/
/* Private functions----------------------------------------------------------*/ /* Private functions----------------------------------------------------------*/
/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions /** @addtogroup TIMEx_Private_Functions TIMEx Private Functions
* @{ * @{
*/ */
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);

View file

@ -340,11 +340,12 @@ __STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
* @arg @ref LL_GPIO_OUTPUT_OPENDRAIN * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType) __STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t OutputType)
{ {
MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType)); MODIFY_REG(GPIOx->OTYPER, (GPIO_OTYPER_OT_0 << POSITION_VAL(Pin)), (OutputType << POSITION_VAL(Pin)));
} }
/** /**
* @brief Return gpio output type for several pins on dedicated port. * @brief Return gpio output type for several pins on dedicated port.
* @note Output type as to be set when gpio pin is in output or * @note Output type as to be set when gpio pin is in output or

View file

@ -357,9 +357,9 @@ typedef struct
* @param __BAUDRATE__ Baud rate value to achieve * @param __BAUDRATE__ Baud rate value to achieve
* @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
*/ */
#define __LL_USART_DIV_SAMPLING8_100(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__)*25)/(2*(__BAUDRATE__))) #define __LL_USART_DIV_SAMPLING8_100(__PERIPHCLK__, __BAUDRATE__) ((uint32_t)((((uint64_t)(__PERIPHCLK__))*25)/(2*((uint64_t)(__BAUDRATE__)))))
#define __LL_USART_DIVMANT_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__))/100) #define __LL_USART_DIVMANT_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__))/100)
#define __LL_USART_DIVFRAQ_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 8 + 50) / 100) #define __LL_USART_DIVFRAQ_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 8) + 50) / 100)
/* UART BRR = mantissa + overflow + fraction /* UART BRR = mantissa + overflow + fraction
= (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07) */ = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07) */
#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \ #define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \
@ -373,9 +373,9 @@ typedef struct
* @param __BAUDRATE__ Baud rate value to achieve * @param __BAUDRATE__ Baud rate value to achieve
* @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
*/ */
#define __LL_USART_DIV_SAMPLING16_100(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__)*25)/(4*(__BAUDRATE__))) #define __LL_USART_DIV_SAMPLING16_100(__PERIPHCLK__, __BAUDRATE__) ((uint32_t)((((uint64_t)(__PERIPHCLK__))*25)/(4*((uint64_t)(__BAUDRATE__)))))
#define __LL_USART_DIVMANT_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__))/100) #define __LL_USART_DIVMANT_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__))/100)
#define __LL_USART_DIVFRAQ_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 16 + 50) / 100) #define __LL_USART_DIVFRAQ_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) ((((__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 16) + 50) / 100)
/* USART BRR = mantissa + overflow + fraction /* USART BRR = mantissa + overflow + fraction
= (USART DIVMANT << 4) + (USART DIVFRAQ & 0xF0) + (USART DIVFRAQ & 0x0F) */ = (USART DIVMANT << 4) + (USART DIVFRAQ & 0xF0) + (USART DIVFRAQ & 0x0F) */
#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \ #define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \

View file

@ -50,11 +50,11 @@
* @{ * @{
*/ */
/** /**
* @brief STM32F4xx HAL Driver version number V1.7.6 * @brief STM32F4xx HAL Driver version number V1.7.7
*/ */
#define __STM32F4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32F4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32F4xx_HAL_VERSION_SUB1 (0x07U) /*!< [23:16] sub1 version */ #define __STM32F4xx_HAL_VERSION_SUB1 (0x07U) /*!< [23:16] sub1 version */
#define __STM32F4xx_HAL_VERSION_SUB2 (0x06U) /*!< [15:8] sub2 version */ #define __STM32F4xx_HAL_VERSION_SUB2 (0x07U) /*!< [15:8] sub2 version */
#define __STM32F4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32F4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F4xx_HAL_VERSION ((__STM32F4xx_HAL_VERSION_MAIN << 24U)\ #define __STM32F4xx_HAL_VERSION ((__STM32F4xx_HAL_VERSION_MAIN << 24U)\
|(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\ |(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\
@ -341,14 +341,26 @@ uint32_t HAL_GetTickPrio(void)
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
{ {
HAL_StatusTypeDef status = HAL_OK; HAL_StatusTypeDef status = HAL_OK;
HAL_TickFreqTypeDef prevTickFreq;
assert_param(IS_TICKFREQ(Freq)); assert_param(IS_TICKFREQ(Freq));
if (uwTickFreq != Freq) if (uwTickFreq != Freq)
{ {
/* Back up uwTickFreq frequency */
prevTickFreq = uwTickFreq;
/* Update uwTickFreq global variable used by HAL_InitTick() */
uwTickFreq = Freq; uwTickFreq = Freq;
/* Apply the new tick Freq */ /* Apply the new tick Freq */
status = HAL_InitTick(uwTickPrio); status = HAL_InitTick(uwTickPrio);
if (status != HAL_OK)
{
/* Restore previous tick frequency */
uwTickFreq = prevTickFreq;
}
} }
return status; return status;
@ -557,7 +569,7 @@ uint32_t HAL_GetUIDw2(void)
/** /**
* @brief Enables the Internal FLASH Bank Swapping. * @brief Enables the Internal FLASH Bank Swapping.
* *
* @note This function can be used only for STM32F42xxx/43xxx devices. * @note This function can be used only for STM32F42xxx/43xxx/469xx/479xx devices.
* *
* @note Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000) * @note Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000)
* and Flash Bank1 mapped at 0x08100000 (and aliased at 0x00100000) * and Flash Bank1 mapped at 0x08100000 (and aliased at 0x00100000)
@ -572,7 +584,7 @@ void HAL_EnableMemorySwappingBank(void)
/** /**
* @brief Disables the Internal FLASH Bank Swapping. * @brief Disables the Internal FLASH Bank Swapping.
* *
* @note This function can be used only for STM32F42xxx/43xxx devices. * @note This function can be used only for STM32F42xxx/43xxx/469xx/479xx devices.
* *
* @note The default state : Flash Bank1 mapped at 0x08000000 (and aliased @0x00000000) * @note The default state : Flash Bank1 mapped at 0x08000000 (and aliased @0x00000000)
* and Flash Bank2 mapped at 0x08100000 (and aliased at 0x00100000) * and Flash Bank2 mapped at 0x08100000 (and aliased at 0x00100000)

View file

@ -0,0 +1,330 @@
/**
******************************************************************************
* @file stm32f4xx_hal_crc.c
* @author MCD Application Team
* @brief CRC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Cyclic Redundancy Check (CRC) peripheral:
* + Initialization and de-initialization functions
* + Peripheral Control functions
* + Peripheral State functions
*
@verbatim
===============================================================================
##### How to use this driver #####
===============================================================================
[..]
(+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
(+) Initialize CRC calculator
(++) specify generating polynomial (peripheral default or non-default one)
(++) specify initialization value (peripheral default or non-default one)
(++) specify input data format
(++) specify input or output data inversion mode if any
(+) Use HAL_CRC_Accumulate() function to compute the CRC value of the
input data buffer starting with the previously computed CRC as
initialization value
(+) Use HAL_CRC_Calculate() function to compute the CRC value of the
input data buffer starting with the defined initialization value
(default or non-default) to initiate CRC calculation
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal.h"
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
/** @defgroup CRC CRC
* @brief CRC HAL module driver.
* @{
*/
#ifdef HAL_CRC_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CRC_Exported_Functions CRC Exported Functions
* @{
*/
/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions.
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize the CRC according to the specified parameters
in the CRC_InitTypeDef and create the associated handle
(+) DeInitialize the CRC peripheral
(+) Initialize the CRC MSP (MCU Specific Package)
(+) DeInitialize the CRC MSP
@endverbatim
* @{
*/
/**
* @brief Initialize the CRC according to the specified
* parameters in the CRC_InitTypeDef and create the associated handle.
* @param hcrc CRC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
{
/* Check the CRC handle allocation */
if (hcrc == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
if (hcrc->State == HAL_CRC_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hcrc->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_CRC_MspInit(hcrc);
}
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief DeInitialize the CRC peripheral.
* @param hcrc CRC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
{
/* Check the CRC handle allocation */
if (hcrc == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
/* Check the CRC peripheral state */
if (hcrc->State == HAL_CRC_STATE_BUSY)
{
return HAL_BUSY;
}
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
/* Reset CRC calculation unit */
__HAL_CRC_DR_RESET(hcrc);
/* Reset IDR register content */
CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR);
/* DeInit the low level hardware */
HAL_CRC_MspDeInit(hcrc);
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_RESET;
/* Process unlocked */
__HAL_UNLOCK(hcrc);
/* Return function status */
return HAL_OK;
}
/**
* @brief Initializes the CRC MSP.
* @param hcrc CRC handle
* @retval None
*/
__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcrc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_CRC_MspInit can be implemented in the user file
*/
}
/**
* @brief DeInitialize the CRC MSP.
* @param hcrc CRC handle
* @retval None
*/
__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcrc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_CRC_MspDeInit can be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
* @brief management functions.
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) compute the 32-bit CRC value of a 32-bit data buffer
using combination of the previous CRC value and the new one.
[..] or
(+) compute the 32-bit CRC value of a 32-bit data buffer
independently of the previous CRC value.
@endverbatim
* @{
*/
/**
* @brief Compute the 32-bit CRC value of a 32-bit data buffer
* starting with the previously computed CRC as initialization value.
* @param hcrc CRC handle
* @param pBuffer pointer to the input data buffer.
* @param BufferLength input data buffer length (number of uint32_t words).
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
*/
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
{
uint32_t index; /* CRC input data buffer index */
uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
/* Enter Data to the CRC calculator */
for (index = 0U; index < BufferLength; index++)
{
hcrc->Instance->DR = pBuffer[index];
}
temp = hcrc->Instance->DR;
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_READY;
/* Return the CRC computed value */
return temp;
}
/**
* @brief Compute the 32-bit CRC value of a 32-bit data buffer
* starting with hcrc->Instance->INIT as initialization value.
* @param hcrc CRC handle
* @param pBuffer pointer to the input data buffer.
* @param BufferLength input data buffer length (number of uint32_t words).
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
*/
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
{
uint32_t index; /* CRC input data buffer index */
uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
/* Reset CRC Calculation Unit (hcrc->Instance->INIT is
* written in hcrc->Instance->DR) */
__HAL_CRC_DR_RESET(hcrc);
/* Enter 32-bit input data to the CRC calculator */
for (index = 0U; index < BufferLength; index++)
{
hcrc->Instance->DR = pBuffer[index];
}
temp = hcrc->Instance->DR;
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_READY;
/* Return the CRC computed value */
return temp;
}
/**
* @}
*/
/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
* @brief Peripheral State functions.
*
@verbatim
===============================================================================
##### Peripheral State functions #####
===============================================================================
[..]
This subsection permits to get in run-time the status of the peripheral.
@endverbatim
* @{
*/
/**
* @brief Return the CRC handle state.
* @param hcrc CRC handle
* @retval HAL state
*/
HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
{
/* Return CRC handle state */
return hcrc->State;
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_CRC_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

View file

@ -478,7 +478,6 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
/* Enable Common interrupts*/ /* Enable Common interrupts*/
hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME; hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
hdma->Instance->FCR |= DMA_IT_FE;
if(hdma->XferHalfCpltCallback != NULL) if(hdma->XferHalfCpltCallback != NULL)
{ {

View file

@ -45,6 +45,8 @@
EXTI_ConfigTypeDef structure. EXTI_ConfigTypeDef structure.
(++) For configurable lines, configure rising and/or falling trigger (++) For configurable lines, configure rising and/or falling trigger
"Trigger" member from EXTI_ConfigTypeDef structure. "Trigger" member from EXTI_ConfigTypeDef structure.
(++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
member from GPIO_InitTypeDef structure.
(#) Get current Exti configuration of a dedicated line using (#) Get current Exti configuration of a dedicated line using
HAL_EXTI_GetConfigLine(). HAL_EXTI_GetConfigLine().
@ -141,6 +143,8 @@
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
{ {
uint32_t regval; uint32_t regval;
uint32_t linepos;
uint32_t maskline;
/* Check null pointer */ /* Check null pointer */
if ((hexti == NULL) || (pExtiConfig == NULL)) if ((hexti == NULL) || (pExtiConfig == NULL))
@ -151,37 +155,77 @@ HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT
/* Check parameters */ /* Check parameters */
assert_param(IS_EXTI_LINE(pExtiConfig->Line)); assert_param(IS_EXTI_LINE(pExtiConfig->Line));
assert_param(IS_EXTI_MODE(pExtiConfig->Mode)); assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
/* Assign line number to handle */ /* Assign line number to handle */
hexti->Line = pExtiConfig->Line; hexti->Line = pExtiConfig->Line;
/* Clear EXTI line configuration */ /* Compute line mask */
EXTI->IMR &= ~pExtiConfig->Line; linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
EXTI->EMR &= ~pExtiConfig->Line; maskline = (1uL << linepos);
/* Select the Mode for the selected external interrupts */ /* Configure triggers for configurable lines */
regval = (uint32_t)EXTI_BASE; if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
regval += pExtiConfig->Mode;
*(__IO uint32_t *) regval |= pExtiConfig->Line;
/* Clear Rising Falling edge configuration */
EXTI->RTSR &= ~pExtiConfig->Line;
EXTI->FTSR &= ~pExtiConfig->Line;
/* Select the trigger for the selected external interrupts */
if (pExtiConfig->Trigger == EXTI_TRIGGER_RISING_FALLING)
{ {
/* Rising Falling edge */ assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
EXTI->RTSR |= pExtiConfig->Line;
EXTI->FTSR |= pExtiConfig->Line; /* Configure rising trigger */
/* Mask or set line */
if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u)
{
EXTI->RTSR |= maskline;
}
else
{
EXTI->RTSR &= ~maskline;
}
/* Configure falling trigger */
/* Mask or set line */
if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u)
{
EXTI->FTSR |= maskline;
}
else
{
EXTI->FTSR &= ~maskline;
}
/* Configure gpio port selection in case of gpio exti line */
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
{
assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
assert_param(IS_EXTI_GPIO_PIN(linepos));
regval = SYSCFG->EXTICR[linepos >> 2u];
regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
SYSCFG->EXTICR[linepos >> 2u] = regval;
}
}
/* Configure interrupt mode : read current mode */
/* Mask or set line */
if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u)
{
EXTI->IMR |= maskline;
} }
else else
{ {
regval = (uint32_t)EXTI_BASE; EXTI->IMR &= ~maskline;
regval += pExtiConfig->Trigger;
*(__IO uint32_t *) regval |= pExtiConfig->Line;
} }
/* Configure event mode : read current mode */
/* Mask or set line */
if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u)
{
EXTI->EMR |= maskline;
}
else
{
EXTI->EMR &= ~maskline;
}
return HAL_OK; return HAL_OK;
} }
@ -193,6 +237,10 @@ HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT
*/ */
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
{ {
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
/* Check null pointer */ /* Check null pointer */
if ((hexti == NULL) || (pExtiConfig == NULL)) if ((hexti == NULL) || (pExtiConfig == NULL))
{ {
@ -205,41 +253,67 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT
/* Store handle line number to configuration structure */ /* Store handle line number to configuration structure */
pExtiConfig->Line = hexti->Line; pExtiConfig->Line = hexti->Line;
/* Get EXTI mode to configiguration structure */ /* Compute line mask */
if ((EXTI->IMR & hexti->Line) == hexti->Line) linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
maskline = (1uL << linepos);
/* 1] Get core mode : interrupt */
/* Check if selected line is enable */
if ((EXTI->IMR & maskline) != 0x00u)
{ {
pExtiConfig->Mode = EXTI_MODE_INTERRUPT; pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
} }
else if ((EXTI->EMR & hexti->Line) == hexti->Line)
{
pExtiConfig->Mode = EXTI_MODE_EVENT;
}
else else
{ {
/* No MODE selected */ pExtiConfig->Mode = EXTI_MODE_NONE;
pExtiConfig->Mode = 0x0Bu;
} }
/* Get EXTI Trigger to configiguration structure */ /* Get event mode */
if ((EXTI->RTSR & hexti->Line) == hexti->Line) /* Check if selected line is enable */
if ((EXTI->EMR & maskline) != 0x00u)
{ {
if ((EXTI->FTSR & hexti->Line) == hexti->Line) pExtiConfig->Mode |= EXTI_MODE_EVENT;
{ }
pExtiConfig->Trigger = EXTI_TRIGGER_RISING_FALLING;
} /* 2] Get trigger for configurable lines : rising */
else if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
{
/* Check if configuration of selected line is enable */
if ((EXTI->RTSR & maskline) != 0x00u)
{ {
pExtiConfig->Trigger = EXTI_TRIGGER_RISING; pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
} }
} else
else if ((EXTI->FTSR & hexti->Line) == hexti->Line) {
{ pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
pExtiConfig->Trigger = EXTI_TRIGGER_FALLING; }
/* Get falling configuration */
/* Check if configuration of selected line is enable */
if ((EXTI->FTSR & maskline) != 0x00u)
{
pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
}
/* Get Gpio port selection for gpio lines */
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
{
assert_param(IS_EXTI_GPIO_PIN(linepos));
regval = SYSCFG->EXTICR[linepos >> 2u];
pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24);
}
else
{
pExtiConfig->GPIOSel = 0x00u;
}
} }
else else
{ {
/* No Trigger selected */ /* No Trigger selected */
pExtiConfig->Trigger = 0x00u; pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
pExtiConfig->GPIOSel = 0x00u;
} }
return HAL_OK; return HAL_OK;
@ -252,6 +326,10 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT
*/ */
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
{ {
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
/* Check null pointer */ /* Check null pointer */
if (hexti == NULL) if (hexti == NULL)
{ {
@ -261,15 +339,32 @@ HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
/* Check the parameter */ /* Check the parameter */
assert_param(IS_EXTI_LINE(hexti->Line)); assert_param(IS_EXTI_LINE(hexti->Line));
/* compute line mask */
linepos = (hexti->Line & EXTI_PIN_MASK);
maskline = (1uL << linepos);
/* 1] Clear interrupt mode */ /* 1] Clear interrupt mode */
EXTI->IMR = (EXTI->IMR & ~hexti->Line); EXTI->IMR = (EXTI->IMR & ~maskline);
/* 2] Clear event mode */ /* 2] Clear event mode */
EXTI->EMR = (EXTI->EMR & ~hexti->Line); EXTI->EMR = (EXTI->EMR & ~maskline);
/* 3] Clear triggers */ /* 3] Clear triggers in case of configurable lines */
EXTI->RTSR = (EXTI->RTSR & ~hexti->Line); if ((hexti->Line & EXTI_CONFIG) != 0x00u)
EXTI->FTSR = (EXTI->FTSR & ~hexti->Line); {
EXTI->RTSR = (EXTI->RTSR & ~maskline);
EXTI->FTSR = (EXTI->FTSR & ~maskline);
/* Get Gpio port selection for gpio lines */
if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
{
assert_param(IS_EXTI_GPIO_PIN(linepos));
regval = SYSCFG->EXTICR[linepos >> 2u];
regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
SYSCFG->EXTICR[linepos >> 2u] = regval;
}
}
return HAL_OK; return HAL_OK;
} }
@ -289,7 +384,7 @@ HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_Call
switch (CallbackID) switch (CallbackID)
{ {
case HAL_EXTI_COMMON_CB_ID: case HAL_EXTI_COMMON_CB_ID:
hexti->RisingCallback = pPendingCbfn; hexti->PendingCallback = pPendingCbfn;
break; break;
default: default:
@ -349,15 +444,23 @@ HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLin
*/ */
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
{ {
if (EXTI->PR != 0x00u) uint32_t regval;
uint32_t maskline;
/* Compute line mask */
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
/* Get pending bit */
regval = (EXTI->PR & maskline);
if (regval != 0x00u)
{ {
/* Clear pending bit */ /* Clear pending bit */
EXTI->PR = hexti->Line; EXTI->PR = maskline;
/* Call callback */ /* Call callback */
if (hexti->RisingCallback != NULL) if (hexti->PendingCallback != NULL)
{ {
hexti->RisingCallback(); hexti->PendingCallback();
} }
} }
} }
@ -373,19 +476,21 @@ void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
*/ */
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
{ {
__IO uint32_t *regaddr;
uint32_t regval; uint32_t regval;
uint32_t linepos;
uint32_t maskline;
/* Check parameters */ /* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line)); assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
assert_param(IS_EXTI_PENDING_EDGE(Edge)); assert_param(IS_EXTI_PENDING_EDGE(Edge));
/* Get pending bit */ /* Compute line mask */
regaddr = &EXTI->PR; linepos = (hexti->Line & EXTI_PIN_MASK);
maskline = (1uL << linepos);
/* return 1 if bit is set else 0 */ /* return 1 if bit is set else 0 */
regval = ((*regaddr & hexti->Line) >> POSITION_VAL(hexti->Line)); regval = ((EXTI->PR & maskline) >> linepos);
return regval; return regval;
} }
@ -400,11 +505,18 @@ uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
*/ */
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
{ {
uint32_t maskline;
/* Check parameters */ /* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line)); assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
assert_param(IS_EXTI_PENDING_EDGE(Edge)); assert_param(IS_EXTI_PENDING_EDGE(Edge));
EXTI->PR = hexti->Line; /* Compute line mask */
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
/* Clear Pending bit */
EXTI->PR = maskline;
} }
/** /**
@ -414,10 +526,17 @@ void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
*/ */
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
{ {
uint32_t maskline;
/* Check parameters */ /* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line)); assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
EXTI->SWIER = hexti->Line; /* Compute line mask */
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
/* Generate Software interrupt */
EXTI->SWIER = maskline;
} }
/** /**

View file

@ -619,8 +619,14 @@ static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD; FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD;
FLASH->CR |= FLASH_CR_PG; FLASH->CR |= FLASH_CR_PG;
/* Program the double-word */ /* Program first word */
*(__IO uint32_t*)Address = (uint32_t)Data; *(__IO uint32_t*)Address = (uint32_t)Data;
/* Barrier to ensure programming is performed in 2 steps, in right order
(independently of compiler optimization behavior) */
__ISB();
/* Program second word */
*(__IO uint32_t*)(Address+4) = (uint32_t)(Data >> 32); *(__IO uint32_t*)(Address+4) = (uint32_t)(Data >> 32);
} }

View file

@ -192,24 +192,6 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
if(iocurrent == ioposition) if(iocurrent == ioposition)
{ {
/*--------------------- GPIO Mode Configuration ------------------------*/ /*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Alternate function mode selection */
if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
{
/* Check the Alternate function parameter */
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3U];
temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
GPIOx->AFR[position >> 3U] = temp;
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
GPIOx->MODER = temp;
/* In case of Output or Alternate function mode selection */ /* In case of Output or Alternate function mode selection */
if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
@ -227,7 +209,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
temp &= ~(GPIO_OTYPER_OT_0 << position) ; temp &= ~(GPIO_OTYPER_OT_0 << position) ;
temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position); temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
GPIOx->OTYPER = temp; GPIOx->OTYPER = temp;
} }
/* Activate the Pull-up or Pull down resistor for the current IO */ /* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR; temp = GPIOx->PUPDR;
@ -235,6 +217,24 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
temp |= ((GPIO_Init->Pull) << (position * 2U)); temp |= ((GPIO_Init->Pull) << (position * 2U));
GPIOx->PUPDR = temp; GPIOx->PUPDR = temp;
/* In case of Alternate function mode selection */
if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
{
/* Check the Alternate function parameter */
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3U];
temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
GPIOx->AFR[position >> 3U] = temp;
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
GPIOx->MODER = temp;
/*--------------------- EXTI Mode Configuration ------------------------*/ /*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */ /* Configure the External Interrupt or event for the current IO */
if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
@ -318,10 +318,6 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
tmp &= (0x0FU << (4U * (position & 0x03U))); tmp &= (0x0FU << (4U * (position & 0x03U)));
if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)))) if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))))
{ {
/* Configure the External Interrupt or event for the current IO */
tmp = 0x0FU << (4U * (position & 0x03U));
SYSCFG->EXTICR[position >> 2U] &= ~tmp;
/* Clear EXTI line configuration */ /* Clear EXTI line configuration */
EXTI->IMR &= ~((uint32_t)iocurrent); EXTI->IMR &= ~((uint32_t)iocurrent);
EXTI->EMR &= ~((uint32_t)iocurrent); EXTI->EMR &= ~((uint32_t)iocurrent);
@ -329,6 +325,10 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
/* Clear Rising Falling edge configuration */ /* Clear Rising Falling edge configuration */
EXTI->RTSR &= ~((uint32_t)iocurrent); EXTI->RTSR &= ~((uint32_t)iocurrent);
EXTI->FTSR &= ~((uint32_t)iocurrent); EXTI->FTSR &= ~((uint32_t)iocurrent);
/* Configure the External Interrupt or event for the current IO */
tmp = 0x0FU << (4U * (position & 0x03U));
SYSCFG->EXTICR[position >> 2U] &= ~tmp;
} }
/*------------------------- GPIO Mode Configuration --------------------*/ /*------------------------- GPIO Mode Configuration --------------------*/
@ -338,14 +338,14 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
/* Configure the default Alternate Function in current IO */ /* Configure the default Alternate Function in current IO */
GPIOx->AFR[position >> 3U] &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; GPIOx->AFR[position >> 3U] &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
/* Configure the default value for IO Speed */ /* Deactivate the Pull-up and Pull-down resistor for the current IO */
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
/* Configure the default value IO Output Type */ /* Configure the default value IO Output Type */
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ; GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ;
/* Deactivate the Pull-up and Pull-down resistor for the current IO */ /* Configure the default value for IO Speed */
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
} }
} }
} }
@ -473,9 +473,10 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
GPIOx->LCKR = GPIO_Pin; GPIOx->LCKR = GPIO_Pin;
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
GPIOx->LCKR = tmp; GPIOx->LCKR = tmp;
/* Read LCKK bit*/ /* Read LCKR register. This read is mandatory to complete key lock sequence */
tmp = GPIOx->LCKR; tmp = GPIOx->LCKR;
/* Read again in order to confirm lock is active */
if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET) if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
{ {
return HAL_OK; return HAL_OK;

View file

@ -220,7 +220,7 @@ __weak HAL_StatusTypeDef HAL_RCC_DeInit(void)
*/ */
__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{ {
uint32_t tickstart; uint32_t tickstart, pll_config;
/* Check Null pointer */ /* Check Null pointer */
if(RCC_OscInitStruct == NULL) if(RCC_OscInitStruct == NULL)
@ -531,7 +531,24 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc
} }
else else
{ {
return HAL_ERROR; /* Check if there is a request to disable the PLL used as System clock source */
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
{
return HAL_ERROR;
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->CFGR;
if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != RCC_OscInitStruct->PLL.PLLN) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ))
{
return HAL_ERROR;
}
}
} }
} }
return HAL_OK; return HAL_OK;
@ -693,7 +710,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos]; SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
/* Configure the source of time base considering new system clocks settings */ /* Configure the source of time base considering new system clocks settings */
HAL_InitTick (TICK_INT_PRIORITY); HAL_InitTick (uwTickPrio);
return HAL_OK; return HAL_OK;
} }

View file

@ -2175,7 +2175,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division
factor is common parameters for both peripherals */ factor is common parameters for both peripherals */
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S)) (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S) ||
(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))
{ {
/* check for Parameters */ /* check for Parameters */
assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
@ -2227,6 +2228,17 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
} }
/*----------------- In Case of PLLI2S is just selected -----------------*/
if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
{
/* Check for Parameters */
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
/* Configure the PLLI2S multiplication and division factors */
__HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
}
/* Enable the PLLI2S */ /* Enable the PLLI2S */
__HAL_RCC_PLLI2S_ENABLE(); __HAL_RCC_PLLI2S_ENABLE();
/* Get tick */ /* Get tick */
@ -2472,7 +2484,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U))); frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
break; break;
} }
/* Clock not enabled for I2S */ /* Clock not enabled for I2S*/
default: default:
{ {
frequency = 0U; frequency = 0U;
@ -3292,7 +3304,7 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
SystemCoreClock = HSI_VALUE; SystemCoreClock = HSI_VALUE;
/* Adapt Systick interrupt period */ /* Adapt Systick interrupt period */
if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) if(HAL_InitTick(uwTickPrio) != HAL_OK)
{ {
return HAL_ERROR; return HAL_ERROR;
} }

View file

@ -98,18 +98,22 @@
*** Callback registration *** *** Callback registration ***
============================================= =============================================
[..]
The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1 The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks. allows the user to configure dynamically the driver callbacks.
[..]
Use Function @ref HAL_TIM_RegisterCallback() to register a callback. Use Function @ref HAL_TIM_RegisterCallback() to register a callback.
@ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
the Callback ID and a pointer to the user callback function. the Callback ID and a pointer to the user callback function.
[..]
Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default
weak function. weak function.
@ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID. and the Callback ID.
[..]
These functions allow to register/unregister following callbacks: These functions allow to register/unregister following callbacks:
(+) Base_MspInitCallback : TIM Base Msp Init Callback. (+) Base_MspInitCallback : TIM Base Msp Init Callback.
(+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback. (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback.
@ -139,15 +143,18 @@
(+) CommutationHalfCpltCallback : TIM Commutation half complete Callback. (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback.
(+) BreakCallback : TIM Break Callback. (+) BreakCallback : TIM Break Callback.
[..]
By default, after the Init and when the state is HAL_TIM_STATE_RESET By default, after the Init and when the state is HAL_TIM_STATE_RESET
all interrupt callbacks are set to the corresponding weak functions: all interrupt callbacks are set to the corresponding weak functions:
examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback(). examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback().
[..]
Exception done for MspInit and MspDeInit functions that are reset to the legacy weak Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
functionalities in the Init / DeInit only when these callbacks are null functionalities in the Init / DeInit only when these callbacks are null
(not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
keep and use the user MspInit / MspDeInit callbacks(registered beforehand) keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
[..]
Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only. Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
Exception done MspInit / MspDeInit that can be registered / unregistered Exception done MspInit / MspDeInit that can be registered / unregistered
in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state, in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
@ -155,6 +162,7 @@ all interrupt callbacks are set to the corresponding weak functions:
In that case first register the MspInit/MspDeInit user callbacks In that case first register the MspInit/MspDeInit user callbacks
using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function. using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.
[..]
When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions. are set to the corresponding weak functions.
@ -213,7 +221,7 @@ static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
TIM_SlaveConfigTypeDef *sSlaveConfig); TIM_SlaveConfigTypeDef *sSlaveConfig);
/** /**
* @} * @}
*/ */
@ -224,8 +232,8 @@ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
*/ */
/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions /** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
* @brief Time Base functions * @brief Time Base functions
* *
@verbatim @verbatim
============================================================================== ==============================================================================
##### Time Base functions ##### ##### Time Base functions #####
@ -479,11 +487,11 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
if ((htim->State == HAL_TIM_STATE_BUSY)) if (htim->State == HAL_TIM_STATE_BUSY)
{ {
return HAL_BUSY; return HAL_BUSY;
} }
else if ((htim->State == HAL_TIM_STATE_READY)) else if (htim->State == HAL_TIM_STATE_READY)
{ {
if ((pData == NULL) && (Length > 0U)) if ((pData == NULL) && (Length > 0U))
{ {
@ -556,8 +564,8 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
*/ */
/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions /** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
* @brief TIM Output Compare functions * @brief TIM Output Compare functions
* *
@verbatim @verbatim
============================================================================== ==============================================================================
##### TIM Output Compare functions ##### ##### TIM Output Compare functions #####
@ -922,16 +930,16 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
*/ */
HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
{ {
uint32_t tmpsmcr; uint32_t tmpsmcr;
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
if ((htim->State == HAL_TIM_STATE_BUSY)) if (htim->State == HAL_TIM_STATE_BUSY)
{ {
return HAL_BUSY; return HAL_BUSY;
} }
else if ((htim->State == HAL_TIM_STATE_READY)) else if (htim->State == HAL_TIM_STATE_READY)
{ {
if ((pData == NULL) && (Length > 0U)) if ((pData == NULL) && (Length > 0U))
{ {
@ -1129,8 +1137,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
*/ */
/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions /** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
* @brief TIM PWM functions * @brief TIM PWM functions
* *
@verbatim @verbatim
============================================================================== ==============================================================================
##### TIM PWM functions ##### ##### TIM PWM functions #####
@ -1502,11 +1510,11 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
if ((htim->State == HAL_TIM_STATE_BUSY)) if (htim->State == HAL_TIM_STATE_BUSY)
{ {
return HAL_BUSY; return HAL_BUSY;
} }
else if ((htim->State == HAL_TIM_STATE_READY)) else if (htim->State == HAL_TIM_STATE_READY)
{ {
if ((pData == NULL) && (Length > 0U)) if ((pData == NULL) && (Length > 0U))
{ {
@ -1703,8 +1711,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
*/ */
/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions /** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
* @brief TIM Input Capture functions * @brief TIM Input Capture functions
* *
@verbatim @verbatim
============================================================================== ==============================================================================
##### TIM Input Capture functions ##### ##### TIM Input Capture functions #####
@ -2050,11 +2058,11 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
if ((htim->State == HAL_TIM_STATE_BUSY)) if (htim->State == HAL_TIM_STATE_BUSY)
{ {
return HAL_BUSY; return HAL_BUSY;
} }
else if ((htim->State == HAL_TIM_STATE_READY)) else if (htim->State == HAL_TIM_STATE_READY)
{ {
if ((pData == NULL) && (Length > 0U)) if ((pData == NULL) && (Length > 0U))
{ {
@ -2238,8 +2246,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
*/ */
/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions /** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
* @brief TIM One Pulse functions * @brief TIM One Pulse functions
* *
@verbatim @verbatim
============================================================================== ==============================================================================
##### TIM One Pulse functions ##### ##### TIM One Pulse functions #####
@ -2552,8 +2560,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out
*/ */
/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions /** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
* @brief TIM Encoder functions * @brief TIM Encoder functions
* *
@verbatim @verbatim
============================================================================== ==============================================================================
##### TIM Encoder functions ##### ##### TIM Encoder functions #####
@ -2605,8 +2613,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini
assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity)); assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
@ -2955,16 +2963,17 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan
* @param Length The length of data to be transferred from TIM peripheral to memory. * @param Length The length of data to be transferred from TIM peripheral to memory.
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length) HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
uint32_t *pData2, uint16_t Length)
{ {
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
if ((htim->State == HAL_TIM_STATE_BUSY)) if (htim->State == HAL_TIM_STATE_BUSY)
{ {
return HAL_BUSY; return HAL_BUSY;
} }
else if ((htim->State == HAL_TIM_STATE_READY)) else if (htim->State == HAL_TIM_STATE_READY)
{ {
if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U)) if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
{ {
@ -3138,8 +3147,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
* @} * @}
*/ */
/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
* @brief TIM IRQ handler management * @brief TIM IRQ handler management
* *
@verbatim @verbatim
============================================================================== ==============================================================================
##### IRQ handler management ##### ##### IRQ handler management #####
@ -3339,8 +3348,8 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
*/ */
/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
* @brief TIM Peripheral Control functions * @brief TIM Peripheral Control functions
* *
@verbatim @verbatim
============================================================================== ==============================================================================
##### Peripheral Control functions ##### ##### Peripheral Control functions #####
@ -3656,9 +3665,14 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @note To output a waveform with a minimum delay user can enable the fast
* mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
* output is forced in response to the edge detection on TIx input,
* without taking in account the comparison.
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel) HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
uint32_t OutputChannel, uint32_t InputChannel)
{ {
TIM_OC_InitTypeDef temp1; TIM_OC_InitTypeDef temp1;
@ -3805,11 +3819,11 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
assert_param(IS_TIM_DMA_LENGTH(BurstLength)); assert_param(IS_TIM_DMA_LENGTH(BurstLength));
if ((htim->State == HAL_TIM_STATE_BUSY)) if (htim->State == HAL_TIM_STATE_BUSY)
{ {
return HAL_BUSY; return HAL_BUSY;
} }
else if ((htim->State == HAL_TIM_STATE_READY)) else if (htim->State == HAL_TIM_STATE_READY)
{ {
if ((BurstBuffer == NULL) && (BurstLength > 0U)) if ((BurstBuffer == NULL) && (BurstLength > 0U))
{ {
@ -3852,7 +3866,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */ /* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
(uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
{ {
return HAL_ERROR; return HAL_ERROR;
} }
@ -3868,7 +3883,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */ /* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
(uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
{ {
return HAL_ERROR; return HAL_ERROR;
} }
@ -3884,7 +3900,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */ /* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
(uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
{ {
return HAL_ERROR; return HAL_ERROR;
} }
@ -3900,7 +3917,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */ /* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
(uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
{ {
return HAL_ERROR; return HAL_ERROR;
} }
@ -3916,7 +3934,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */ /* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
(uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
{ {
return HAL_ERROR; return HAL_ERROR;
} }
@ -3932,7 +3951,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */ /* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
(uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
{ {
return HAL_ERROR; return HAL_ERROR;
} }
@ -4055,8 +4075,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B
* @note This function should be used only when BurstLength is equal to DMA data transfer length. * @note This function should be used only when BurstLength is equal to DMA data transfer length.
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t *BurstBuffer, uint32_t BurstLength) uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
{ {
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
@ -4064,11 +4084,11 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
assert_param(IS_TIM_DMA_LENGTH(BurstLength)); assert_param(IS_TIM_DMA_LENGTH(BurstLength));
if ((htim->State == HAL_TIM_STATE_BUSY)) if (htim->State == HAL_TIM_STATE_BUSY)
{ {
return HAL_BUSY; return HAL_BUSY;
} }
else if ((htim->State == HAL_TIM_STATE_READY)) else if (htim->State == HAL_TIM_STATE_READY)
{ {
if ((BurstBuffer == NULL) && (BurstLength > 0U)) if ((BurstBuffer == NULL) && (BurstLength > 0U))
{ {
@ -4366,7 +4386,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
/* When OCRef clear feature is used with ETR source, ETR prescaler must be off */ /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1) if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
{ {
htim->State = HAL_TIM_STATE_READY; htim->State = HAL_TIM_STATE_READY;
__HAL_UNLOCK(htim); __HAL_UNLOCK(htim);
return HAL_ERROR; return HAL_ERROR;
} }
@ -4653,9 +4673,9 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveC
htim->State = HAL_TIM_STATE_BUSY; htim->State = HAL_TIM_STATE_BUSY;
if(TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
{ {
htim->State = HAL_TIM_STATE_READY; htim->State = HAL_TIM_STATE_READY;
__HAL_UNLOCK(htim); __HAL_UNLOCK(htim);
return HAL_ERROR; return HAL_ERROR;
} }
@ -4683,7 +4703,7 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveC
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
TIM_SlaveConfigTypeDef *sSlaveConfig) TIM_SlaveConfigTypeDef *sSlaveConfig)
{ {
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
@ -4694,9 +4714,9 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
htim->State = HAL_TIM_STATE_BUSY; htim->State = HAL_TIM_STATE_BUSY;
if(TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
{ {
htim->State = HAL_TIM_STATE_READY; htim->State = HAL_TIM_STATE_READY;
__HAL_UNLOCK(htim); __HAL_UNLOCK(htim);
return HAL_ERROR; return HAL_ERROR;
} }
@ -4786,8 +4806,8 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
*/ */
/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
* @brief TIM Callbacks functions * @brief TIM Callbacks functions
* *
@verbatim @verbatim
============================================================================== ==============================================================================
##### TIM Callbacks functions ##### ##### TIM Callbacks functions #####
@ -4990,7 +5010,8 @@ __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
* @param pCallback pointer to the callback function * @param pCallback pointer to the callback function
* @retval status * @retval status
*/ */
HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback) HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
pTIM_CallbackTypeDef pCallback)
{ {
HAL_StatusTypeDef status = HAL_OK; HAL_StatusTypeDef status = HAL_OK;
@ -5441,8 +5462,8 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca
*/ */
/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
* @brief TIM Peripheral State functions * @brief TIM Peripheral State functions
* *
@verbatim @verbatim
============================================================================== ==============================================================================
##### Peripheral State functions ##### ##### Peripheral State functions #####
@ -6121,7 +6142,7 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
* @retval None * @retval None
*/ */
static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
TIM_SlaveConfigTypeDef *sSlaveConfig) TIM_SlaveConfigTypeDef *sSlaveConfig)
{ {
uint32_t tmpsmcr; uint32_t tmpsmcr;
uint32_t tmpccmr1; uint32_t tmpccmr1;

View file

@ -72,7 +72,7 @@
* opensource.org/licenses/BSD-3-Clause * opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal.h" #include "stm32f4xx_hal.h"
@ -396,11 +396,11 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
if ((htim->State == HAL_TIM_STATE_BUSY)) if (htim->State == HAL_TIM_STATE_BUSY)
{ {
return HAL_BUSY; return HAL_BUSY;
} }
else if ((htim->State == HAL_TIM_STATE_READY)) else if (htim->State == HAL_TIM_STATE_READY)
{ {
if (((uint32_t)pData == 0U) && (Length > 0U)) if (((uint32_t)pData == 0U) && (Length > 0U))
{ {
@ -708,11 +708,11 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
if ((htim->State == HAL_TIM_STATE_BUSY)) if (htim->State == HAL_TIM_STATE_BUSY)
{ {
return HAL_BUSY; return HAL_BUSY;
} }
else if ((htim->State == HAL_TIM_STATE_READY)) else if (htim->State == HAL_TIM_STATE_READY)
{ {
if (((uint32_t)pData == 0U) && (Length > 0U)) if (((uint32_t)pData == 0U) && (Length > 0U))
{ {
@ -1116,11 +1116,11 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
if ((htim->State == HAL_TIM_STATE_BUSY)) if (htim->State == HAL_TIM_STATE_BUSY)
{ {
return HAL_BUSY; return HAL_BUSY;
} }
else if ((htim->State == HAL_TIM_STATE_READY)) else if (htim->State == HAL_TIM_STATE_READY)
{ {
if (((uint32_t)pData == 0U) && (Length > 0U)) if (((uint32_t)pData == 0U) && (Length > 0U))
{ {
@ -1464,7 +1464,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t
* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
uint32_t CommutationSource)
{ {
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
@ -1519,7 +1520,8 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t
* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
uint32_t CommutationSource)
{ {
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
@ -1575,7 +1577,8 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32
* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
uint32_t CommutationSource)
{ {
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
@ -1630,7 +1633,7 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
uint32_t tmpsmcr; uint32_t tmpsmcr;
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance)); assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
@ -1651,16 +1654,19 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
/* Select the TRGO source */ /* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger; tmpcr2 |= sMasterConfig->MasterOutputTrigger;
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
/* Update TIMx CR2 */ /* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2; htim->Instance->CR2 = tmpcr2;
/* Update TIMx SMCR */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
htim->Instance->SMCR = tmpsmcr; {
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
}
/* Change the htim state */ /* Change the htim state */
htim->State = HAL_TIM_STATE_READY; htim->State = HAL_TIM_STATE_READY;
@ -1676,6 +1682,9 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
* @param htim TIM handle * @param htim TIM handle
* @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
* contains the BDTR Register configuration information for the TIM peripheral. * contains the BDTR Register configuration information for the TIM peripheral.
* @note Interrupts can be generated when an active level is detected on the
* break input, the break 2 input or the system break input. Break
* interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
@ -1886,7 +1895,7 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
*/ */
/* Private functions ---------------------------------------------------------*/ /* Private functions ---------------------------------------------------------*/
/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions /** @defgroup TIMEx_Private_Functions TIMEx Private Functions
* @{ * @{
*/ */

View file

@ -220,8 +220,6 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru
if (currentpin) if (currentpin)
{ {
/* Pin Mode configuration */
LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
{ {
@ -230,6 +228,12 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru
/* Speed mode configuration */ /* Speed mode configuration */
LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed); LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
/* Check Output mode parameters */
assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
/* Output mode configuration*/
LL_GPIO_SetPinOutputType(GPIOx, currentpin, GPIO_InitStruct->OutputType);
} }
/* Pull-up Pull down resistor configuration*/ /* Pull-up Pull down resistor configuration*/
@ -250,19 +254,13 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru
LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate); LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate);
} }
} }
/* Pin Mode configuration */
LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
} }
pinpos++; pinpos++;
} }
if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
{
/* Check Output mode parameters */
assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
/* Output mode configuration*/
LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType);
}
return (SUCCESS); return (SUCCESS);
} }

View file

@ -185,7 +185,7 @@ uint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void);
*/ */
ErrorStatus LL_RCC_DeInit(void) ErrorStatus LL_RCC_DeInit(void)
{ {
uint32_t vl_mask = 0U; __IO uint32_t vl_mask;
/* Set HSION bit */ /* Set HSION bit */
LL_RCC_HSI_Enable(); LL_RCC_HSI_Enable();
@ -197,10 +197,12 @@ ErrorStatus LL_RCC_DeInit(void)
/* Reset CFGR register */ /* Reset CFGR register */
LL_RCC_WriteReg(CFGR, 0x00000000U); LL_RCC_WriteReg(CFGR, 0x00000000U);
vl_mask = 0xFFFFFFFFU; /* Read CR register */
vl_mask = LL_RCC_ReadReg(CR);
/* Reset HSEON, PLLSYSON bits */ /* Reset HSEON, HSEBYP, PLLON, CSSON bits */
CLEAR_BIT(vl_mask, (RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_PLLON | RCC_CR_CSSON)); CLEAR_BIT(vl_mask,
(RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_PLLON | RCC_CR_CSSON));
#if defined(RCC_PLLSAI_SUPPORT) #if defined(RCC_PLLSAI_SUPPORT)
/* Reset PLLSAION bit */ /* Reset PLLSAION bit */
@ -212,7 +214,7 @@ ErrorStatus LL_RCC_DeInit(void)
CLEAR_BIT(vl_mask, RCC_CR_PLLI2SON); CLEAR_BIT(vl_mask, RCC_CR_PLLI2SON);
#endif /* RCC_PLLI2S_SUPPORT */ #endif /* RCC_PLLI2S_SUPPORT */
/* Write new mask in CR register */ /* Write new value in CR register */
LL_RCC_WriteReg(CR, vl_mask); LL_RCC_WriteReg(CR, vl_mask);
/* Set HSITRIM bits to the reset value*/ /* Set HSITRIM bits to the reset value*/

View file

@ -346,13 +346,13 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini
#if defined(UART9) #if defined(UART9)
else if (USARTx == UART9) else if (USARTx == UART9)
{ {
periphclk = rcc_clocks.PCLK1_Frequency; periphclk = rcc_clocks.PCLK2_Frequency;
} }
#endif /* UART9 */ #endif /* UART9 */
#if defined(UART10) #if defined(UART10)
else if (USARTx == UART10) else if (USARTx == UART10)
{ {
periphclk = rcc_clocks.PCLK1_Frequency; periphclk = rcc_clocks.PCLK2_Frequency;
} }
#endif /* UART10 */ #endif /* UART10 */
else else

View file

@ -13,7 +13,29 @@ Dma.MEMTOMEM.0.PeriphInc=DMA_PINC_DISABLE
Dma.MEMTOMEM.0.Priority=DMA_PRIORITY_LOW Dma.MEMTOMEM.0.Priority=DMA_PRIORITY_LOW
Dma.MEMTOMEM.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst Dma.MEMTOMEM.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst
Dma.Request0=MEMTOMEM Dma.Request0=MEMTOMEM
Dma.RequestsNb=1 Dma.Request1=USART1_RX
Dma.Request2=USART1_TX
Dma.RequestsNb=3
Dma.USART1_RX.1.Direction=DMA_PERIPH_TO_MEMORY
Dma.USART1_RX.1.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.USART1_RX.1.Instance=DMA2_Stream2
Dma.USART1_RX.1.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.USART1_RX.1.MemInc=DMA_MINC_ENABLE
Dma.USART1_RX.1.Mode=DMA_NORMAL
Dma.USART1_RX.1.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.USART1_RX.1.PeriphInc=DMA_PINC_DISABLE
Dma.USART1_RX.1.Priority=DMA_PRIORITY_LOW
Dma.USART1_RX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
Dma.USART1_TX.2.Direction=DMA_MEMORY_TO_PERIPH
Dma.USART1_TX.2.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.USART1_TX.2.Instance=DMA2_Stream7
Dma.USART1_TX.2.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.USART1_TX.2.MemInc=DMA_MINC_ENABLE
Dma.USART1_TX.2.Mode=DMA_NORMAL
Dma.USART1_TX.2.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.USART1_TX.2.PeriphInc=DMA_PINC_DISABLE
Dma.USART1_TX.2.Priority=DMA_PRIORITY_LOW
Dma.USART1_TX.2.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
FSMC.AddressSetupTime1=0 FSMC.AddressSetupTime1=0
FSMC.BusTurnAroundDuration1=0 FSMC.BusTurnAroundDuration1=0
FSMC.DataSetupTime1=1 FSMC.DataSetupTime1=1
@ -21,13 +43,14 @@ FSMC.IPParameters=DataSetupTime1,AddressSetupTime1,BusTurnAroundDuration1
File.Version=6 File.Version=6
KeepUserPlacement=false KeepUserPlacement=false
Mcu.Family=STM32F4 Mcu.Family=STM32F4
Mcu.IP0=DMA Mcu.IP0=CRC
Mcu.IP1=FSMC Mcu.IP1=DMA
Mcu.IP2=NVIC Mcu.IP2=FSMC
Mcu.IP3=RCC Mcu.IP3=NVIC
Mcu.IP4=SYS Mcu.IP4=RCC
Mcu.IP5=USART1 Mcu.IP5=SYS
Mcu.IPNb=6 Mcu.IP6=USART1
Mcu.IPNb=7
Mcu.Name=STM32F407V(E-G)Tx Mcu.Name=STM32F407V(E-G)Tx
Mcu.Package=LQFP100 Mcu.Package=LQFP100
Mcu.Pin0=PE3 Mcu.Pin0=PE3
@ -57,22 +80,26 @@ Mcu.Pin3=PH1-OSC_OUT
Mcu.Pin30=PD7 Mcu.Pin30=PD7
Mcu.Pin31=PB3 Mcu.Pin31=PB3
Mcu.Pin32=PB4 Mcu.Pin32=PB4
Mcu.Pin33=VP_SYS_VS_Systick Mcu.Pin33=VP_CRC_VS_CRC
Mcu.Pin34=VP_SYS_VS_Systick
Mcu.Pin4=PA6 Mcu.Pin4=PA6
Mcu.Pin5=PA7 Mcu.Pin5=PA7
Mcu.Pin6=PE7 Mcu.Pin6=PE7
Mcu.Pin7=PE8 Mcu.Pin7=PE8
Mcu.Pin8=PE9 Mcu.Pin8=PE9
Mcu.Pin9=PE10 Mcu.Pin9=PE10
Mcu.PinsNb=34 Mcu.PinsNb=35
Mcu.ThirdPartyNb=0 Mcu.ThirdPartyNb=0
Mcu.UserConstants= Mcu.UserConstants=
Mcu.UserName=STM32F407VETx Mcu.UserName=STM32F407VETx
MxCube.Version=5.3.0 MxCube.Version=5.5.0
MxDb.Version=DB.5.0.30 MxDb.Version=DB.5.0.50
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.DMA2_Stream2_IRQn=true\:0\:0\:false\:false\:true\:false\:true
NVIC.DMA2_Stream4_IRQn=true\:0\:0\:false\:false\:true\:true\:true NVIC.DMA2_Stream4_IRQn=true\:0\:0\:false\:false\:true\:true\:true
NVIC.DMA2_Stream7_IRQn=true\:0\:0\:false\:false\:true\:false\:true
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.ForceEnableDMAVector=true
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
@ -175,7 +202,7 @@ ProjectManager.CustomerFirmwarePackage=
ProjectManager.DefaultFWLocation=true ProjectManager.DefaultFWLocation=true
ProjectManager.DeletePrevious=true ProjectManager.DeletePrevious=true
ProjectManager.DeviceId=STM32F407VETx ProjectManager.DeviceId=STM32F407VETx
ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.24.1 ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.24.2
ProjectManager.FreePins=false ProjectManager.FreePins=false
ProjectManager.HalAssertFull=false ProjectManager.HalAssertFull=false
ProjectManager.HeapSize=0x200 ProjectManager.HeapSize=0x200
@ -228,6 +255,8 @@ RCC.VCOOutputFreq_Value=336000000
RCC.VcooutputI2S=192000000 RCC.VcooutputI2S=192000000
USART1.IPParameters=VirtualMode USART1.IPParameters=VirtualMode
USART1.VirtualMode=VM_ASYNC USART1.VirtualMode=VM_ASYNC
VP_CRC_VS_CRC.Mode=CRC_Activate
VP_CRC_VS_CRC.Signal=CRC_VS_CRC
VP_SYS_VS_Systick.Mode=SysTick VP_SYS_VS_Systick.Mode=SysTick
VP_SYS_VS_Systick.Signal=SYS_VS_Systick VP_SYS_VS_Systick.Signal=SYS_VS_Systick
board=custom board=custom

58
Inc/crc.h Normal file
View file

@ -0,0 +1,58 @@
/**
******************************************************************************
* File Name : CRC.h
* Description : This file provides code for the configuration
* of the CRC instances.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __crc_H
#define __crc_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
extern CRC_HandleTypeDef hcrc;
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
void MX_CRC_Init(void);
/* USER CODE BEGIN Prototypes */
/* USER CODE END Prototypes */
#ifdef __cplusplus
}
#endif
#endif /*__ crc_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

View file

@ -6,7 +6,7 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.</center></h2>
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software component is licensed by ST under BSD 3-Clause license,

View file

@ -6,7 +6,7 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.</center></h2>
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software component is licensed by ST under BSD 3-Clause license,

View file

@ -6,7 +6,7 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.</center></h2>
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software component is licensed by ST under BSD 3-Clause license,

View file

@ -3,9 +3,9 @@
* @file stm32_assert.h * @file stm32_assert.h
* @brief STM32 assert file. * @brief STM32 assert file.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.</center></h2>
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software component is licensed by ST under BSD 3-Clause license,

View file

@ -39,7 +39,7 @@
/* #define HAL_ADC_MODULE_ENABLED */ /* #define HAL_ADC_MODULE_ENABLED */
/* #define HAL_CRYP_MODULE_ENABLED */ /* #define HAL_CRYP_MODULE_ENABLED */
/* #define HAL_CAN_MODULE_ENABLED */ /* #define HAL_CAN_MODULE_ENABLED */
/* #define HAL_CRC_MODULE_ENABLED */ #define HAL_CRC_MODULE_ENABLED
/* #define HAL_CRYP_MODULE_ENABLED */ /* #define HAL_CRYP_MODULE_ENABLED */
/* #define HAL_DAC_MODULE_ENABLED */ /* #define HAL_DAC_MODULE_ENABLED */
/* #define HAL_DCMI_MODULE_ENABLED */ /* #define HAL_DCMI_MODULE_ENABLED */
@ -66,6 +66,7 @@
/* #define HAL_USART_MODULE_ENABLED */ /* #define HAL_USART_MODULE_ENABLED */
/* #define HAL_IRDA_MODULE_ENABLED */ /* #define HAL_IRDA_MODULE_ENABLED */
/* #define HAL_SMARTCARD_MODULE_ENABLED */ /* #define HAL_SMARTCARD_MODULE_ENABLED */
/* #define HAL_SMBUS_MODULE_ENABLED */
/* #define HAL_WWDG_MODULE_ENABLED */ /* #define HAL_WWDG_MODULE_ENABLED */
/* #define HAL_PCD_MODULE_ENABLED */ /* #define HAL_PCD_MODULE_ENABLED */
/* #define HAL_HCD_MODULE_ENABLED */ /* #define HAL_HCD_MODULE_ENABLED */
@ -77,7 +78,6 @@
/* #define HAL_SPDIFRX_MODULE_ENABLED */ /* #define HAL_SPDIFRX_MODULE_ENABLED */
/* #define HAL_DFSDM_MODULE_ENABLED */ /* #define HAL_DFSDM_MODULE_ENABLED */
/* #define HAL_LPTIM_MODULE_ENABLED */ /* #define HAL_LPTIM_MODULE_ENABLED */
/* #define HAL_EXTI_MODULE_ENABLED */
#define HAL_GPIO_MODULE_ENABLED #define HAL_GPIO_MODULE_ENABLED
#define HAL_EXTI_MODULE_ENABLED #define HAL_EXTI_MODULE_ENABLED
#define HAL_DMA_MODULE_ENABLED #define HAL_DMA_MODULE_ENABLED
@ -264,6 +264,10 @@
#include "stm32f4xx_hal_cryp.h" #include "stm32f4xx_hal_cryp.h"
#endif /* HAL_CRYP_MODULE_ENABLED */ #endif /* HAL_CRYP_MODULE_ENABLED */
#ifdef HAL_SMBUS_MODULE_ENABLED
#include "stm32f4xx_hal_smbus.h"
#endif /* HAL_SMBUS_MODULE_ENABLED */
#ifdef HAL_DMA2D_MODULE_ENABLED #ifdef HAL_DMA2D_MODULE_ENABLED
#include "stm32f4xx_hal_dma2d.h" #include "stm32f4xx_hal_dma2d.h"
#endif /* HAL_DMA2D_MODULE_ENABLED */ #endif /* HAL_DMA2D_MODULE_ENABLED */

View file

@ -57,7 +57,9 @@ void DebugMon_Handler(void);
void PendSV_Handler(void); void PendSV_Handler(void);
void SysTick_Handler(void); void SysTick_Handler(void);
void USART1_IRQHandler(void); void USART1_IRQHandler(void);
void DMA2_Stream2_IRQHandler(void);
void DMA2_Stream4_IRQHandler(void); void DMA2_Stream4_IRQHandler(void);
void DMA2_Stream7_IRQHandler(void);
/* USER CODE BEGIN EFP */ /* USER CODE BEGIN EFP */
/* USER CODE END EFP */ /* USER CODE END EFP */

View file

@ -6,7 +6,7 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.</center></h2>
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software component is licensed by ST under BSD 3-Clause license,

View file

@ -56,8 +56,8 @@ ENTRY(Reset_Handler)
/* Highest address of the user mode stack */ /* Highest address of the user mode stack */
_estack = 0x20020000; /* end of "RAM" Ram type memory */ _estack = 0x20020000; /* end of "RAM" Ram type memory */
_Min_Heap_Size = 0x200; /* required amount of heap */ _Min_Heap_Size = 0x200 ; /* required amount of heap */
_Min_Stack_Size = 0x400; /* required amount of stack */ _Min_Stack_Size = 0x400 ; /* required amount of stack */
/* Memories definition */ /* Memories definition */
MEMORY MEMORY

77
Src/crc.c Normal file
View file

@ -0,0 +1,77 @@
/**
******************************************************************************
* File Name : CRC.c
* Description : This file provides code for the configuration
* of the CRC instances.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "crc.h"
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
CRC_HandleTypeDef hcrc;
/* CRC init function */
void MX_CRC_Init(void)
{
hcrc.Instance = CRC;
if (HAL_CRC_Init(&hcrc) != HAL_OK)
{
Error_Handler();
}
}
void HAL_CRC_MspInit(CRC_HandleTypeDef* crcHandle)
{
if(crcHandle->Instance==CRC)
{
/* USER CODE BEGIN CRC_MspInit 0 */
/* USER CODE END CRC_MspInit 0 */
/* CRC clock enable */
__HAL_RCC_CRC_CLK_ENABLE();
/* USER CODE BEGIN CRC_MspInit 1 */
/* USER CODE END CRC_MspInit 1 */
}
}
void HAL_CRC_MspDeInit(CRC_HandleTypeDef* crcHandle)
{
if(crcHandle->Instance==CRC)
{
/* USER CODE BEGIN CRC_MspDeInit 0 */
/* USER CODE END CRC_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_CRC_CLK_DISABLE();
/* USER CODE BEGIN CRC_MspDeInit 1 */
/* USER CODE END CRC_MspDeInit 1 */
}
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

View file

@ -6,7 +6,7 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.</center></h2>
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software component is licensed by ST under BSD 3-Clause license,
@ -81,9 +81,15 @@ void MX_DMA_Init(void)
LL_DMA_SetPeriphBurstxfer(DMA2, LL_DMA_STREAM_4, LL_DMA_PBURST_SINGLE); LL_DMA_SetPeriphBurstxfer(DMA2, LL_DMA_STREAM_4, LL_DMA_PBURST_SINGLE);
/* DMA interrupt init */ /* DMA interrupt init */
/* DMA2_Stream2_IRQn interrupt configuration */
NVIC_SetPriority(DMA2_Stream2_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
NVIC_EnableIRQ(DMA2_Stream2_IRQn);
/* DMA2_Stream4_IRQn interrupt configuration */ /* DMA2_Stream4_IRQn interrupt configuration */
NVIC_SetPriority(DMA2_Stream4_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); NVIC_SetPriority(DMA2_Stream4_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
NVIC_EnableIRQ(DMA2_Stream4_IRQn); NVIC_EnableIRQ(DMA2_Stream4_IRQn);
/* DMA2_Stream7_IRQn interrupt configuration */
NVIC_SetPriority(DMA2_Stream7_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
NVIC_EnableIRQ(DMA2_Stream7_IRQn);
} }

View file

@ -6,7 +6,7 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.</center></h2>
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software component is licensed by ST under BSD 3-Clause license,
@ -78,6 +78,7 @@ static void HAL_FSMC_MspInit(void){
return; return;
} }
FSMC_Initialized = 1; FSMC_Initialized = 1;
/* Peripheral clock enable */ /* Peripheral clock enable */
__HAL_RCC_FSMC_CLK_ENABLE(); __HAL_RCC_FSMC_CLK_ENABLE();

View file

@ -6,7 +6,7 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.</center></h2>
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software component is licensed by ST under BSD 3-Clause license,

View file

@ -20,6 +20,7 @@
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "main.h" #include "main.h"
#include "crc.h"
#include "dma.h" #include "dma.h"
#include "usart.h" #include "usart.h"
#include "gpio.h" #include "gpio.h"
@ -27,7 +28,7 @@
/* Private includes ----------------------------------------------------------*/ /* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */ /* USER CODE BEGIN Includes */
#include <mainloop.h> #include <application.h>
/* USER CODE END Includes */ /* USER CODE END Includes */
@ -95,10 +96,13 @@ int main(void)
MX_DMA_Init(); MX_DMA_Init();
MX_USART1_UART_Init(); MX_USART1_UART_Init();
MX_FSMC_Init(); MX_FSMC_Init();
MX_CRC_Init();
/* USER CODE BEGIN 2 */ /* USER CODE BEGIN 2 */
MainLoop(); MainLoop();
/* USER CODE END 2 */ /* USER CODE END 2 */
/* Infinite loop */ /* Infinite loop */
/* USER CODE BEGIN WHILE */ /* USER CODE BEGIN WHILE */
while (1) while (1)

View file

@ -205,13 +205,27 @@ void SysTick_Handler(void)
void USART1_IRQHandler(void) void USART1_IRQHandler(void)
{ {
/* USER CODE BEGIN USART1_IRQn 0 */ /* USER CODE BEGIN USART1_IRQn 0 */
HandleConsoleUsartIrq();
/* USER CODE END USART1_IRQn 0 */ /* USER CODE END USART1_IRQn 0 */
/* USER CODE BEGIN USART1_IRQn 1 */ /* USER CODE BEGIN USART1_IRQn 1 */
/* USER CODE END USART1_IRQn 1 */ /* USER CODE END USART1_IRQn 1 */
} }
/**
* @brief This function handles DMA2 stream2 global interrupt.
*/
void DMA2_Stream2_IRQHandler(void)
{
/* USER CODE BEGIN DMA2_Stream2_IRQn 0 */
HandleConsoleRxDmaIrq();
/* USER CODE END DMA2_Stream2_IRQn 0 */
/* USER CODE BEGIN DMA2_Stream2_IRQn 1 */
/* USER CODE END DMA2_Stream2_IRQn 1 */
}
/** /**
* @brief This function handles DMA2 stream4 global interrupt. * @brief This function handles DMA2 stream4 global interrupt.
*/ */
@ -226,6 +240,20 @@ void DMA2_Stream4_IRQHandler(void)
/* USER CODE END DMA2_Stream4_IRQn 1 */ /* USER CODE END DMA2_Stream4_IRQn 1 */
} }
/**
* @brief This function handles DMA2 stream7 global interrupt.
*/
void DMA2_Stream7_IRQHandler(void)
{
/* USER CODE BEGIN DMA2_Stream7_IRQn 0 */
HandleConsoleTxDmaIrq();
/* USER CODE END DMA2_Stream7_IRQn 0 */
/* USER CODE BEGIN DMA2_Stream7_IRQn 1 */
/* USER CODE END DMA2_Stream7_IRQn 1 */
}
/* USER CODE BEGIN 1 */ /* USER CODE BEGIN 1 */
/* USER CODE END 1 */ /* USER CODE END 1 */

View file

@ -6,7 +6,7 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.</center></h2>
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software component is licensed by ST under BSD 3-Clause license,
@ -31,6 +31,7 @@ void MX_USART1_UART_Init(void)
LL_USART_InitTypeDef USART_InitStruct = {0}; LL_USART_InitTypeDef USART_InitStruct = {0};
LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
/* Peripheral clock enable */ /* Peripheral clock enable */
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1); LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1);
@ -43,10 +44,50 @@ void MX_USART1_UART_Init(void)
GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
GPIO_InitStruct.Pull = LL_GPIO_PULL_UP; GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
GPIO_InitStruct.Alternate = LL_GPIO_AF_7; GPIO_InitStruct.Alternate = LL_GPIO_AF_7;
LL_GPIO_Init(GPIOA, &GPIO_InitStruct); LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/* USART1 DMA Init */
/* USART1_RX Init */
LL_DMA_SetChannelSelection(DMA2, LL_DMA_STREAM_2, LL_DMA_CHANNEL_4);
LL_DMA_SetDataTransferDirection(DMA2, LL_DMA_STREAM_2, LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
LL_DMA_SetStreamPriorityLevel(DMA2, LL_DMA_STREAM_2, LL_DMA_PRIORITY_LOW);
LL_DMA_SetMode(DMA2, LL_DMA_STREAM_2, LL_DMA_MODE_NORMAL);
LL_DMA_SetPeriphIncMode(DMA2, LL_DMA_STREAM_2, LL_DMA_PERIPH_NOINCREMENT);
LL_DMA_SetMemoryIncMode(DMA2, LL_DMA_STREAM_2, LL_DMA_MEMORY_INCREMENT);
LL_DMA_SetPeriphSize(DMA2, LL_DMA_STREAM_2, LL_DMA_PDATAALIGN_BYTE);
LL_DMA_SetMemorySize(DMA2, LL_DMA_STREAM_2, LL_DMA_MDATAALIGN_BYTE);
LL_DMA_DisableFifoMode(DMA2, LL_DMA_STREAM_2);
/* USART1_TX Init */
LL_DMA_SetChannelSelection(DMA2, LL_DMA_STREAM_7, LL_DMA_CHANNEL_4);
LL_DMA_SetDataTransferDirection(DMA2, LL_DMA_STREAM_7, LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
LL_DMA_SetStreamPriorityLevel(DMA2, LL_DMA_STREAM_7, LL_DMA_PRIORITY_LOW);
LL_DMA_SetMode(DMA2, LL_DMA_STREAM_7, LL_DMA_MODE_NORMAL);
LL_DMA_SetPeriphIncMode(DMA2, LL_DMA_STREAM_7, LL_DMA_PERIPH_NOINCREMENT);
LL_DMA_SetMemoryIncMode(DMA2, LL_DMA_STREAM_7, LL_DMA_MEMORY_INCREMENT);
LL_DMA_SetPeriphSize(DMA2, LL_DMA_STREAM_7, LL_DMA_PDATAALIGN_BYTE);
LL_DMA_SetMemorySize(DMA2, LL_DMA_STREAM_7, LL_DMA_MDATAALIGN_BYTE);
LL_DMA_DisableFifoMode(DMA2, LL_DMA_STREAM_7);
/* USART1 interrupt Init */ /* USART1 interrupt Init */
NVIC_SetPriority(USART1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); NVIC_SetPriority(USART1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
NVIC_EnableIRQ(USART1_IRQn); NVIC_EnableIRQ(USART1_IRQn);

View file

@ -0,0 +1,190 @@
/*
* interrupt.c
*
* Created on: Aug 29, 2019
* Author: abody
*/
#include <f4ll_cpp/crcscheduler.h>
#include <string.h>
#if defined(HAVE_DIAG)
#include "diag.h"
#endif
#include "f4ll_cpp/dmahelper.h"
#ifndef DIAG_CRC_CALC_START
# define DIAG_CRC_CALC_START()
#endif
#ifndef DIAG_CRC_CALC_END
# define DIAG_CRC_CALC_END()
#endif
#ifndef DIAG_INTERRUPT_IN
# define DIAG_INTERRUPT_IN()
#endif
#ifndef DIAG_INTERRUPT_OUT
# define DIAG_INTERRUPT_OUT()
#endif
void Crc_StartNextTask(struct crcstatus_t *status);
CrcScheduler::CrcScheduler(CRC_TypeDef *crcUnit, DMA_TypeDef *dma, uint32_t stream) :
m_dma(dma, stream),
m_activeSlot(nullptr),
m_firstSlot(nullptr)
{
m_crcUnit = crcUnit;
LL_DMA_EnableIT_TC(dma, stream);
LL_DMA_EnableIT_TE(dma, stream);
LL_DMA_SetM2MDstAddress(dma, stream, (uint32_t)&crcUnit->DR);
}
void CrcScheduler::AttachTasks(struct crcslot_t *slot, struct crctask_t *tasks, uint8_t taskCount)
{
slot->count = taskCount;
slot->tasks = tasks;
memset(tasks, 0, sizeof(*tasks)*taskCount);
uint32_t prim = __get_PRIMASK();
__disable_irq();
slot->next = m_firstSlot;
m_firstSlot = slot;
__set_PRIMASK(prim);
}
uint8_t CrcScheduler::GetActiveTask(struct crcslot_t **slot_out)
{
uint8_t ret;
uint32_t prim = __get_PRIMASK();
__disable_irq();
ret = m_activeTask;
if(slot_out)
*slot_out = (struct crcslot_t *) m_activeSlot;
__set_PRIMASK(prim);
return ret;
}
bool CrcScheduler::IsTaskQueued(struct crcslot_t *slot, uint8_t task) {
return ((struct crctask_t volatile)slot->tasks[task]).address != NULL;
}
bool CrcScheduler::IsTaskBusy(struct crcslot_t *slot, uint8_t task) {
struct crctask_t volatile *taskPtr = &slot->tasks[task];
return taskPtr->callback != NULL || taskPtr->callbackParam != NULL;
}
void CrcScheduler::WaitResults(struct crcslot_t *slot, uint8_t task) {
while(IsTaskBusy(slot, task));
}
uint8_t CrcScheduler::Enqueue(struct crcslot_t *slot, uint8_t task, void *address, uint16_t len,
ICrcCallback* callback, void* callbackParam)
{
uint32_t prim = __get_PRIMASK();
bool need_start;
//struct crcstatus_t volatile *st = status;
while(IsTaskBusy(slot, task));
__disable_irq();
need_start = (m_activeSlot == nullptr);
slot->tasks[task].address = need_start ? NULL : address;
slot->tasks[task].wordCount = (len+3)/4;
slot->tasks[task].callback = callback;
slot->tasks[task].callbackParam = callbackParam;
if(need_start) {
m_activeSlot = slot;
m_activeTask = task;
}
__set_PRIMASK(prim);
if(need_start) {
DIAG_CRC_CALC_START();
m_crcUnit->CR = 1;
LL_DMA_SetM2MSrcAddress(m_dma.GetDma(), m_dma.GetStream(), (uint32_t)address);
LL_DMA_SetDataLength(m_dma.GetDma(), m_dma.GetStream(), (len+3)/4);
DIAG_CRC_CALC_START();
LL_DMA_EnableStream(m_dma.GetDma(), m_dma.GetStream());
}
return need_start;
}
uint32_t CrcScheduler::Compute(struct crcslot_t *slot, uint8_t task, void *address, uint16_t len)
{
uint32_t result;
Enqueue(slot, task, address, len, NULL, &result);
while((struct crcslot_t volatile *)slot->tasks[task].callbackParam);
return result;
}
// only called from ISR context
void CrcScheduler::StartNextTask()
{
char moreTasks;
uint8_t index = 0;
do {
struct crcslot_t *slot = m_firstSlot;
moreTasks = 0;
while(slot) {
if(index < slot->count) {
if(slot->tasks[index].address) {
DIAG_CRC_CALC_START();
m_activeSlot = slot;
m_activeTask = index;
m_crcUnit->CR = 1;
LL_DMA_SetM2MSrcAddress(m_dma.GetDma(), m_dma.GetStream(), (uint32_t)slot->tasks[index].address);
LL_DMA_SetDataLength(m_dma.GetDma(), m_dma.GetStream(), slot->tasks[index].wordCount);
LL_DMA_EnableStream(m_dma.GetDma(), m_dma.GetStream());
slot->tasks[index].address = nullptr; // marking as started
return;
}
if(index + 1 < slot->count)
moreTasks = 1;
}
slot = slot->next;
}
++index;
} while(moreTasks);
m_activeSlot = nullptr;
}
// !!!PORTABILITY WARNING!!! using registers and bits directly. should be reviewed extremely when porting to a different MCU
void CrcScheduler::_HandleDmaIrq()
{
uint8_t success = 1;
DIAG_INTERRUPT_IN();
if((*m_dma.GetIsReg() & m_dma.GetTcMask()) ||
(*m_dma.GetIsReg() & m_dma.GetTeMask())) {
if(*m_dma.GetIsReg() & m_dma.GetTeMask())
success = 0;
*m_dma.GetIfcReg() = *m_dma.GetIsReg() & (m_dma.GetTcMask() | m_dma.GetTeMask());
LL_DMA_DisableStream(m_dma.GetDma(), m_dma.GetStream());
if(m_activeSlot) {
crctask_t *tsk = &m_activeSlot->tasks[m_activeTask];
if(tsk->callback)
tsk->callback->CrcCalculationCompleted(tsk->callbackParam, m_crcUnit->DR, success);
else if(tsk->callbackParam)
*(uint32_t*)tsk->callbackParam = success ? m_crcUnit->DR : 0xffffffff;
tsk->callback = nullptr;
tsk->callbackParam = nullptr; // marking as inactive
DIAG_CRC_CALC_END();
StartNextTask();
}
}
DIAG_INTERRUPT_OUT();
}

View file

@ -0,0 +1,68 @@
/*
* interrupt.h
*
* Created on: Aug 29, 2019
* Author: abody
*/
#ifndef CRC_HANDLER_H_
#define CRC_HANDLER_H_
#include <inttypes.h>
#ifdef HAVE_CONFIG
#include "config.h"
#endif // HAVE_CONFIG
#include <platform/crc_ll.h>
#include <f4ll_cpp/dmahelper.h>
class CrcScheduler {
public:
struct ICrcCallback {
virtual void CrcCalculationCompleted(void*, uint32_t, uint8_t) = 0;
};
struct crctask_t {
void * volatile address;
uint16_t wordCount;
ICrcCallback* callback;
void *callbackParam;
};
struct crcslot_t {
uint16_t count;
struct crcslot_t *next;
struct crctask_t *tasks;
};
CrcScheduler(CRC_TypeDef *crcUnit, DMA_TypeDef *dma, uint32_t stream);
uint8_t GetActiveTask(struct crcslot_t **slot_out);
bool IsTaskQueued(struct crcslot_t *slot, uint8_t task);
bool IsTaskBusy(struct crcslot_t *slot, uint8_t task);
void WaitResults(struct crcslot_t *slot, uint8_t task);
void AttachTasks(struct crcslot_t *slot, struct crctask_t *tasks, uint8_t taskCount);
uint8_t Enqueue(struct crcslot_t *slot, uint8_t task, void *address, uint16_t len,
ICrcCallback* callback, void* callbackParam);
uint32_t Compute(struct crcslot_t *slot, uint8_t task, void *address, uint16_t len);
static void HandleDmaIrq(void *param) { reinterpret_cast<CrcScheduler*>(param)->_HandleDmaIrq(); }
void _HandleDmaIrq();
private:
void StartNextTask();
CRC_TypeDef *m_crcUnit;
DmaHelper m_dma;
volatile crcslot_t *m_activeSlot;
volatile uint8_t m_activeTask;
crcslot_t *m_firstSlot;
};
#endif /* CRC_HANDLER_H_ */

View file

@ -13,16 +13,16 @@ DmaHelper::DmaHelper(DMA_TypeDef *dma, uint32_t stream)
{ {
m_dma = dma; m_dma = dma;
m_stream = stream; m_stream = stream;
m_isReg = GetIsReg(dma, stream); m_isReg = _GetIsReg(dma, stream);
m_ifcReg = GetIfcReg(dma, stream); m_ifcReg = _GetIfcReg(dma, stream);
m_feMask = GetFeMask(stream); m_feMask = _GetFeMask(stream);
m_dmeMask = GetDmeMask(stream); m_dmeMask = _GetDmeMask(stream);
m_teMask = GetTeMask(stream); m_teMask = _GetTeMask(stream);
m_htMask = GetHtMask(stream); m_htMask = _GetHtMask(stream);
m_tcMask = GetTcMask(stream); m_tcMask = _GetTcMask(stream);
} }
volatile uint32_t* DmaHelper::GetIsReg(DMA_TypeDef *dma, uint32_t stream) volatile uint32_t* DmaHelper::_GetIsReg(DMA_TypeDef *dma, uint32_t stream)
{ {
if(dma == DMA1) if(dma == DMA1)
return (stream < LL_DMA_STREAM_4) ? &DMA1->LISR : &DMA1->HISR; return (stream < LL_DMA_STREAM_4) ? &DMA1->LISR : &DMA1->HISR;
@ -31,7 +31,7 @@ volatile uint32_t* DmaHelper::GetIsReg(DMA_TypeDef *dma, uint32_t stream)
} }
volatile uint32_t* DmaHelper::GetIfcReg(DMA_TypeDef *dma, uint32_t stream) volatile uint32_t* DmaHelper::_GetIfcReg(DMA_TypeDef *dma, uint32_t stream)
{ {
if(dma == DMA1) if(dma == DMA1)
return (stream < LL_DMA_STREAM_4) ? &DMA1->LIFCR : &DMA1->HIFCR; return (stream < LL_DMA_STREAM_4) ? &DMA1->LIFCR : &DMA1->HIFCR;
@ -39,7 +39,7 @@ volatile uint32_t* DmaHelper::GetIfcReg(DMA_TypeDef *dma, uint32_t stream)
return (stream < LL_DMA_STREAM_4) ? &DMA2->LIFCR : &DMA2->HIFCR; return (stream < LL_DMA_STREAM_4) ? &DMA2->LIFCR : &DMA2->HIFCR;
} }
uint32_t DmaHelper::GetFeMask(uint32_t stream) uint32_t DmaHelper::_GetFeMask(uint32_t stream)
{ {
static const uint32_t feMasks[8] = { static const uint32_t feMasks[8] = {
DMA_LISR_FEIF0, DMA_LISR_FEIF1, DMA_LISR_FEIF2, DMA_LISR_FEIF3, DMA_HISR_FEIF4, DMA_HISR_FEIF5, DMA_HISR_FEIF6, DMA_HISR_FEIF7 DMA_LISR_FEIF0, DMA_LISR_FEIF1, DMA_LISR_FEIF2, DMA_LISR_FEIF3, DMA_HISR_FEIF4, DMA_HISR_FEIF5, DMA_HISR_FEIF6, DMA_HISR_FEIF7
@ -47,7 +47,7 @@ uint32_t DmaHelper::GetFeMask(uint32_t stream)
return feMasks[stream]; return feMasks[stream];
} }
uint32_t DmaHelper::GetDmeMask(uint32_t stream) uint32_t DmaHelper::_GetDmeMask(uint32_t stream)
{ {
static const uint32_t dmeMasks[8] = { static const uint32_t dmeMasks[8] = {
DMA_LISR_DMEIF0, DMA_LISR_DMEIF1, DMA_LISR_DMEIF2, DMA_LISR_DMEIF3, DMA_HISR_DMEIF4, DMA_HISR_DMEIF5, DMA_HISR_DMEIF6, DMA_HISR_DMEIF7 DMA_LISR_DMEIF0, DMA_LISR_DMEIF1, DMA_LISR_DMEIF2, DMA_LISR_DMEIF3, DMA_HISR_DMEIF4, DMA_HISR_DMEIF5, DMA_HISR_DMEIF6, DMA_HISR_DMEIF7
@ -55,7 +55,7 @@ uint32_t DmaHelper::GetDmeMask(uint32_t stream)
return dmeMasks[stream]; return dmeMasks[stream];
} }
uint32_t DmaHelper::GetTeMask(uint32_t stream) uint32_t DmaHelper::_GetTeMask(uint32_t stream)
{ {
static const uint32_t teMasks[8] = { static const uint32_t teMasks[8] = {
DMA_LISR_TEIF0, DMA_LISR_TEIF1, DMA_LISR_TEIF2, DMA_LISR_TEIF3, DMA_HISR_TEIF4, DMA_HISR_TEIF5, DMA_HISR_TEIF6, DMA_HISR_TEIF7 DMA_LISR_TEIF0, DMA_LISR_TEIF1, DMA_LISR_TEIF2, DMA_LISR_TEIF3, DMA_HISR_TEIF4, DMA_HISR_TEIF5, DMA_HISR_TEIF6, DMA_HISR_TEIF7
@ -63,7 +63,7 @@ uint32_t DmaHelper::GetTeMask(uint32_t stream)
return teMasks[stream]; return teMasks[stream];
} }
uint32_t DmaHelper::GetHtMask(uint32_t stream) uint32_t DmaHelper::_GetHtMask(uint32_t stream)
{ {
static const uint32_t htMasks[8] = { static const uint32_t htMasks[8] = {
DMA_LISR_HTIF0, DMA_LISR_HTIF1, DMA_LISR_HTIF2, DMA_LISR_HTIF3, DMA_HISR_HTIF4, DMA_HISR_HTIF5, DMA_HISR_HTIF6, DMA_HISR_HTIF7 DMA_LISR_HTIF0, DMA_LISR_HTIF1, DMA_LISR_HTIF2, DMA_LISR_HTIF3, DMA_HISR_HTIF4, DMA_HISR_HTIF5, DMA_HISR_HTIF6, DMA_HISR_HTIF7
@ -71,7 +71,7 @@ uint32_t DmaHelper::GetHtMask(uint32_t stream)
return htMasks[stream]; return htMasks[stream];
} }
uint32_t DmaHelper::GetTcMask(uint32_t stream) uint32_t DmaHelper::_GetTcMask(uint32_t stream)
{ {
static const uint32_t tcMasks[8] = { static const uint32_t tcMasks[8] = {
DMA_LISR_TCIF0, DMA_LISR_TCIF1, DMA_LISR_TCIF2, DMA_LISR_TCIF3, DMA_HISR_TCIF4, DMA_HISR_TCIF5, DMA_HISR_TCIF6, DMA_HISR_TCIF7 DMA_LISR_TCIF0, DMA_LISR_TCIF1, DMA_LISR_TCIF2, DMA_LISR_TCIF3, DMA_HISR_TCIF4, DMA_HISR_TCIF5, DMA_HISR_TCIF6, DMA_HISR_TCIF7

View file

@ -17,13 +17,25 @@
class DmaHelper { class DmaHelper {
public: public:
DmaHelper(DMA_TypeDef *dma, uint32_t stream); DmaHelper(DMA_TypeDef *dma, uint32_t stream);
volatile uint32_t* GetIsReg(DMA_TypeDef *dma, uint32_t stream);
volatile uint32_t* GetIfcReg(DMA_TypeDef *dma, uint32_t stream); DMA_TypeDef* GetDma() { return m_dma; }
uint32_t GetDmeMask(uint32_t stream); uint32_t GetStream() { return m_stream; }
uint32_t GetTeMask(uint32_t stream); volatile uint32_t* GetIsReg() { return m_isReg; }
uint32_t GetHtMask(uint32_t stream); volatile uint32_t* GetIfcReg() { return m_ifcReg; }
uint32_t GetTcMask(uint32_t stream); uint32_t GetDmeMask() { return m_dmeMask; }
uint32_t GetFeMask(uint32_t stream); uint32_t GetTeMask() { return m_teMask; }
uint32_t GetHtMask() { return m_htMask; }
uint32_t GetTcMask() { return m_tcMask; }
uint32_t GetFeMask() { return m_feMask; }
private:
static volatile uint32_t* _GetIsReg(DMA_TypeDef *dma, uint32_t stream);
static volatile uint32_t* _GetIfcReg(DMA_TypeDef *dma, uint32_t stream);
static uint32_t _GetDmeMask(uint32_t stream);
static uint32_t _GetTeMask(uint32_t stream);
static uint32_t _GetHtMask(uint32_t stream);
static uint32_t _GetTcMask(uint32_t stream);
static uint32_t _GetFeMask(uint32_t stream);
private: private:
DMA_TypeDef *m_dma; DMA_TypeDef *m_dma;

View file

@ -0,0 +1,35 @@
/*
* memcpy_dma.c
*
* Created on: Oct 1, 2019
* Author: abody
*/
#include <f4ll_cpp/dmahelper.h>
#include <f4ll_cpp/memcpydma.h>
MemcpyDma::MemcpyDma(DMA_TypeDef *dma, uint32_t stream) :
DmaHelper(dma, stream),
m_busy(false)
{
LL_DMA_EnableIT_TC(dma, stream);
}
void* MemcpyDma::Copy(void *dst, void const *src, size_t length)
{
while(m_busy);
LL_DMA_SetM2MSrcAddress(GetDma(), GetStream(), (uint32_t)src);
LL_DMA_SetM2MDstAddress(GetDma(), GetStream(), (uint32_t)dst);
LL_DMA_SetDataLength(GetDma(), GetStream(), (length+3)/4 );
m_busy = true;
LL_DMA_EnableStream(GetDma(), GetStream());
return dst;
}
void MemcpyDma::HandleDmaIrq(void)
{
if(*GetIsReg() & GetTcMask()) { // DMA transfer complete
*GetIfcReg() = GetTcMask();
LL_DMA_DisableStream(GetDma(), GetStream());
m_busy = false;
}
}

View file

@ -0,0 +1,30 @@
/*
* memcpy_dma.h
*
* Created on: Oct 1, 2019
* Author: abody
*/
#ifndef MEMCPY_DMA_H_
#define MEMCPY_DMA_H_
#include <inttypes.h>
#include <platform/dma_ll.h>
#include <f4ll_cpp/dmahelper.h>
#include <f4ll_cpp/singleton.h>
class MemcpyDma : public DmaHelper, public Singleton<MemcpyDma>
{
public:
MemcpyDma(DMA_TypeDef *dma, uint32_t stream);
void* Copy(void *dst, void const *src, size_t length);
static inline void HandleDmaIrq(void *param) { reinterpret_cast<MemcpyDma*>(param)->HandleDmaIrq(); }
private:
void HandleDmaIrq();
volatile bool m_busy;
};
#endif /* MEMCPY_DMA_H_ */

View file

@ -0,0 +1,282 @@
/*
* usart_handler.c
*
* Created on: Sep 16, 2019
* Author: abody
*/
#include <f4ll_cpp/memcpydma.h>
#include "f4ll_cpp/crcscheduler.h"
#include <f4ll_cpp/packetuart.h>
#include <string.h>
#include <platform/usart_ll.h>
#if defined(HAVE_DIAG)
#include "diag.h"
#endif
#ifndef MOCKABLE
#define MOCKABLE(x) x
#endif
#ifndef DIAG_RX_BUFFER_SWITCH
# define DIAG_RX_BUFFER_SWITCH(x)
#endif
#ifndef DIAG_INTERRUPT_IN
# define DIAG_INTERRUPT_IN()
#endif
#ifndef DIAG_INTERRUPT_OUT
# define DIAG_INTERRUPT_OUT()
#endif
#define STARTMARKER 0x95
static inline uint32_t RoundUpTo4(uint32_t inp)
{
return (inp + 3) & 0xfffc;
}
#ifndef USART_STATS_DISABLED
static inline void StatsIncOverrun(struct usart_stats *s) {
++s->overrun;
}
static inline void StatsIncHdrError(struct usart_stats *s, uint32_t hdr) {
++s->hdrError;
s->lastErrHdr = hdr;
}
static inline void StatsIncPayloadError(struct usart_stats *s, uint32_t pep1, uint32_t pep2) {
++s->payloadErrror;
s->pep1 = pep1;
s->pep2 = pep2;
}
static inline void StatsIncDmaError(struct usart_stats *s) {
++s->dmaError;
}
static inline void StatsIncRcvd(struct usart_stats *s) {
++s->rcvd;
}
static inline void StatsIncPremature_hdr(struct usart_stats *s) {
++s->premature_hdr;
}
static inline void StatsIncPremature_payload(struct usart_stats *s) {
++s->premature_payload;
}
static inline void StatsIncSent(struct usart_stats *s) {
++s->sent;
}
static inline void StatsAddSkiped(struct usart_stats *s, uint8_t cnt) {
s->skiped += s->rcvd > 2 ? cnt : 0;
}
#else // USART_STATS_DISABLED
#define StatsIncOverrun(x)
#define StatsIncHdrError(x,y)
#define StatsIncPayloadError(x,y,z)
#define StatsIncDmaError(x)
#define StatsIncRcvd(x)
#define StatsIncPremature_hdr(x)
#define StatsIncPremature_payload(x)
#define StatsIncSent(x)
#define StatsAddSkiped(x,y)
#endif // USART_STATS_DISABLED
PacketUart::PacketUart(
USART_TypeDef *uart, DMA_TypeDef *dma, uint32_t stream_rx, uint32_t stream_tx, CrcScheduler *crcScheduler,
PacketUart::pku_packetreceivedcallback_t packetReceivedCallback, void * packetReceivedCallbackParam)
: UartBase(uart, dma, stream_rx, stream_tx)
, m_crcScheduler(crcScheduler)
{
uint32_t status = uart->SR;
volatile uint32_t tmpreg = uart->DR; // clearing some of the error/status bits in the USART
(void) tmpreg;
(void) status;
txBuffer.busy = 0;
txBuffer.error = 0;
txBuffer.requestedLength = 0;
rxBuffers[0].busy = 0;
rxBuffers[1].busy = 0;
rxBuffers[0].error = 0;
rxBuffers[1].error = 0;
rxBuffers[0].requestedLength = 0;
rxBuffers[1].requestedLength = 0;
packetReceivedCallback = packetReceivedCallback;
packetReceivedCallbackParam = packetReceivedCallbackParam;
rxSerial = -1;
txSerial = 0;
activeRxBuf = 0;
m_crcScheduler->AttachTasks( &crcSlot, crcTasks, 2);
#ifndef USART_STATS_DISABLED
memset(&st->stats, 0, sizeof(st->stats));
#endif
LL_USART_EnableIT_IDLE(uart);
}
uint8_t* PacketUart::GetTxBuffer()
{
return txBuffer.packet.payload;
}
uint8_t PacketUart::CheckHeader(Packet *packet)
{
return packet->header.startByte == STARTMARKER && (packet->header.startByte ^ packet->header.serial ^ packet->header.payloadLength) == packet->header.hash;
}
uint8_t PacketUart::Post(uint8_t const *payload, uint8_t length, uint8_t waitForCrcQueue)
{
struct Buffer *buffer = &txBuffer;
uint8_t hash = STARTMARKER;
buffer->packet.header.startByte = STARTMARKER;
buffer->packet.header.serial = txSerial;
hash ^= txSerial++;
buffer->packet.header.payloadLength = length;
hash ^= length;
buffer->packet.header.hash = hash;
uint16_t payloadLength = RoundUpTo4(length);
if(payload)
memcpy(txBuffer.packet.payload, payload, length);
txBuffer.requestedLength = sizeof(struct Header) + payloadLength + sizeof(uint32_t); // +4 for the hash
txBuffer.busy = 1;
txBuffer.error = 0;
m_crcScheduler->Enqueue(&crcSlot, 0, &txBuffer.packet, sizeof(txBuffer.packet.header) + payloadLength,
NULL, (uint32_t*)(txBuffer.packet.payload + payloadLength));
while(waitForCrcQueue && m_crcScheduler->IsTaskQueued(&crcSlot, 0));
SetupTransmit(&txBuffer.packet, txBuffer.requestedLength);
StatsIncSent(&status->stats);
return 0;
}
void PacketUart::SetupReceive()
{
uint8_t packetIndex = activeRxBuf;
rxBuffers[packetIndex].requestedLength = sizeof(rxBuffers[packetIndex].packet);
UartBase::SetupReceive(&rxBuffers[packetIndex], sizeof(rxBuffers[packetIndex].packet));
}
void PacketUart::ConsumePacket(uint8_t packetIndex)
{
Buffer *buffer = &rxBuffers[packetIndex];
if(buffer->busy) {
if(buffer->error)
StatsIncPayloadError(&status->stats, Buffer->errorInfo, *(uint32_t*) (Buffer->packet.payload + RoundUpTo4(Buffer->packet.header.payloadLength)));
else {
uint8_t diff = buffer->packet.header.serial - rxSerial;
if(diff > 1)
StatsAddSkiped(&status->stats, diff - 1);
rxSerial = buffer->packet.header.serial;
}
}
buffer->busy = buffer->error = 0;
}
void PacketUart::HandleRxDmaIrq()
{
DIAG_INTERRUPT_IN();
StatsIncRcvd(&status->stats);
if(*m_rxDma.GetIsReg() & m_rxDma.GetTcMask()) {
*m_rxDma.GetIfcReg() = m_rxDma.GetTcMask();
if(CheckHeader(&rxBuffers[activeRxBuf].packet)) {
m_crcScheduler->Enqueue(&crcSlot, 1, &rxBuffers[activeRxBuf].packet,
RoundUpTo4(rxBuffers[activeRxBuf].packet.header.payloadLength) + sizeof(struct Header),
this, &rxBuffers[activeRxBuf]);
} else {
StatsIncHdrError(&status->stats, *(uint32_t*)&status->rxBuffers[status->activeRxBuf].packet.header);
rxBuffers[activeRxBuf].error = 1;
}
}
if(*m_rxDma.GetIsReg() & m_rxDma.GetTeMask()) {
*m_rxDma.GetIfcReg() = m_rxDma.GetTeMask();
rxBuffers[activeRxBuf].error = 1;
}
activeRxBuf ^= 1;
DIAG_RX_BUFFER_SWITCH(status->activeRxBuf);
if(rxBuffers[activeRxBuf].busy)
StatsIncOverrun(&status->stats);
SetupReceive();
DIAG_INTERRUPT_OUT();
}
void PacketUart::CrcCalculationCompleted(void *callbackParm, uint32_t calculatedCrc, uint8_t success)
{
struct Buffer *ub = (struct Buffer*) callbackParm;
if(!success)
ub->error = 1;
else if(*(uint32_t*) (ub->packet.payload + RoundUpTo4(ub->packet.header.payloadLength)) == calculatedCrc)
ub->busy = 1;
else {
ub->error = ub->busy = 1;
ub->errorInfo = calculatedCrc;
}
if(packetReceivedCallback)
packetReceivedCallback(packetReceivedCallbackParam, ub);
}
void PacketUart::HandleTxDmaIrq()
{
DIAG_INTERRUPT_IN();
if(*m_txDma.GetIsReg() & m_txDma.GetTcMask()) { // DMA transfer complete
*m_txDma.GetIfcReg() = m_txDma.GetTcMask();
LL_USART_EnableIT_TC(m_uart);
LL_DMA_DisableStream(m_txDma.GetDma(), m_txDma.GetStream());
}
if(*m_txDma.GetIsReg() & m_txDma.GetTeMask()) {
*m_txDma.GetIfcReg() = m_txDma.GetTeMask();
txBuffer.error = 1;
LL_USART_EnableIT_TC(m_uart);
LL_DMA_DisableStream(m_txDma.GetDma(), m_txDma.GetStream());
StatsIncDmaError(&status->stats);
}
if(*m_txDma.GetIsReg() & m_txDma.GetFeMask())
*m_txDma.GetIfcReg() = m_txDma.GetFeMask();
if(*m_txDma.GetIsReg() & m_txDma.GetHtMask())
*m_txDma.GetIfcReg() = m_txDma.GetHtMask();
if(*m_txDma.GetIsReg() & m_txDma.GetDmeMask())
*m_txDma.GetIfcReg() = m_txDma.GetDmeMask();
DIAG_INTERRUPT_OUT();
}
void PacketUart::HandleUsartIrq()
{
DIAG_INTERRUPT_IN();
if(LL_USART_IsActiveFlag_IDLE(m_uart) && LL_USART_IsEnabledIT_IDLE(m_uart)) { // receiver idle
LL_USART_ClearFlag_IDLE(m_uart);
uint16_t rcvdLen = rxBuffers[activeRxBuf].requestedLength - LL_DMA_GetDataLength(m_rxDma.GetDma(), m_rxDma.GetStream());
if(rcvdLen >= sizeof(struct Header)) {
if(CheckHeader(&rxBuffers[activeRxBuf].packet)) {
if(rcvdLen >= sizeof(struct Header) + RoundUpTo4(rxBuffers[activeRxBuf].packet.header.payloadLength) + sizeof(uint32_t))
LL_DMA_DisableStream(m_rxDma.GetDma(), m_rxDma.GetStream());
else
StatsIncPremature_payload(&stats);
} else {
rxBuffers[activeRxBuf].error = 1;
rxBuffers[activeRxBuf].busy = 1;
LL_DMA_DisableStream(m_rxDma.GetDma(), m_rxDma.GetStream());
}
} else
StatsIncPremature_hdr(&status->stats);
}
if(LL_USART_IsActiveFlag_TC(m_uart) && LL_USART_IsEnabledIT_TC(m_uart)) { // transmission complete
LL_USART_DisableIT_TC(m_uart);
LL_USART_DisableDirectionTx(m_uart); // enforcing an idle frame
LL_USART_EnableDirectionTx(m_uart);
txBuffer.busy = 0;
}
DIAG_INTERRUPT_OUT();
}

View file

@ -0,0 +1,103 @@
/*
* usart_handler.h
*
* Created on: Sep 16, 2019
* Author: abody
*/
#ifndef USART_HANDLER_H_
#define USART_HANDLER_H_
#include <inttypes.h>
#include <platform/usart_ll.h>
#include <f4ll_cpp/uartbase.h>
#define USART_STATS_DISABLED
class PacketUart : public UartBase, public CrcScheduler::ICrcCallback
{
public:
struct Buffer;
struct IPacketUsartCallback {
virtual void PacketReceived(void *userParam, Buffer *buffer) = 0;
};
struct Stats {
uint32_t overrun;
uint32_t hdrError;
uint32_t lastErrHdr;
uint32_t payloadErrror;
uint32_t pep1, pep2;
uint32_t dmaError;
uint32_t rcvd;
uint32_t premature_hdr;
uint32_t premature_payload;
uint32_t sent;
uint32_t skiped;
};
struct Header {
uint8_t startByte;
uint8_t serial;
uint8_t payloadLength;
uint8_t hash;
};
struct Packet {
struct Header header;
//!!! should start on word offset !!!
uint8_t payload[256+sizeof(uint32_t)]; // extra room for crc32
} __attribute__((aligned));
struct Buffer {
Packet packet;
//transfer area ends here
volatile uint8_t busy;
volatile uint8_t error;
uint16_t requestedLength;
uint32_t errorInfo;
};
typedef void (*pku_packetreceivedcallback_t)(void *userParam, Buffer *Buffer);
PacketUart(
USART_TypeDef *uart, DMA_TypeDef *dma, uint32_t stream_rx, uint32_t stream_tx, CrcScheduler *crcScheduler,
PacketUart::pku_packetreceivedcallback_t packetReceivedCallback, void * packetReceivedCallbackParam);
uint8_t* GetTxBuffer();
uint8_t Post(uint8_t const *payload, uint8_t length, uint8_t waitForCrcQueue);
void SetupReceive();
void ConsumePacket(uint8_t packetIndex);
static void HandleRxDmaIrq(void* param) { reinterpret_cast<PacketUart*>(param)->HandleRxDmaIrq(); }
static void HandleTxDmaIrq(void* param) { reinterpret_cast<PacketUart*>(param)->HandleTxDmaIrq(); }
static void HandleUsartIrq(void* param) { reinterpret_cast<PacketUart*>(param)->HandleUsartIrq(); }
uint8_t CheckHeader(struct Packet *packet);
protected:
private:
void HandleRxDmaIrq();
void HandleTxDmaIrq();
void HandleUsartIrq();
virtual void CrcCalculationCompleted(void*, uint32_t, uint8_t);
CrcScheduler *m_crcScheduler;
CrcScheduler::crcslot_t crcSlot;
CrcScheduler::crctask_t crcTasks[2];
uint8_t rxSerial;
uint8_t txSerial;
Stats stats;
uint8_t activeRxBuf;
pku_packetreceivedcallback_t packetReceivedCallback;
void *packetReceivedCallbackParam;
Buffer txBuffer;
Buffer rxBuffers[2];
};
#endif /* UART_HANDLER_H_ */

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/*
* interrupt.h
*
* Created on: Aug 29, 2019
* Author: abody
*/
#ifndef CONSOLEHANDLER_H_
#define CONSOLEHANDLER_H_
#include <cstring>
#include "usart.h"
#include <f4ll_cpp/dmahelper.h>
#include <f4ll_cpp/uartbase.h>
template<unsigned int bufSize> class SerialConsole : protected UartBase
{
public:
struct Buffer {
volatile bool busy = false;
volatile bool error = false;
uint8_t len;
char buffer[bufSize];
};
struct ISerialConsoleCallback {
virtual void LineReceived(void *userParam, Buffer *buffer) = 0;
virtual void TransmissionComplete(void *userParam, Buffer *buffer) = 0;
};
SerialConsole(USART_TypeDef *uart, DMA_TypeDef *dma, uint32_t stream_rx, uint32_t stream_tx,
ISerialConsoleCallback *callback, void *callbackUserParam);
void Send(char const *buffer, uint8_t length = 0);
void SendLine(char const *buffer, uint8_t length = 0);
void HandleRxDmaIrq();
void HandleTxDmaIrq();
void HandleUsartIrq();
private:
bool m_activeRxBuffer = false;
Buffer m_rxBuffers[2];
Buffer m_txBuffer;
ISerialConsoleCallback *m_callback;
void *m_callbackUserParam;
};
template<unsigned int bufSize> SerialConsole<bufSize>::SerialConsole(
USART_TypeDef *uart, DMA_TypeDef *dma, uint32_t stream_rx, uint32_t stream_tx,
ISerialConsoleCallback *callback, void *callbackUserParam
)
: UartBase(uart, dma, stream_rx, stream_tx)
, m_callback(callback), m_callbackUserParam(callbackUserParam)
{
LL_USART_EnableIT_IDLE(uart);
SetupReceive(m_rxBuffers[m_activeRxBuffer].buffer, bufSize);
}
template<unsigned int bufSize> void SerialConsole<bufSize>::HandleRxDmaIrq()
{
if(*m_rxDma.GetIsReg() & m_rxDma.GetTcMask()) {
*m_rxDma.GetIfcReg() = m_rxDma.GetTcMask();
m_rxBuffers[m_activeRxBuffer].busy = true;
if(m_callback)
m_callback->LineReceived(m_callbackUserParam, &m_rxBuffers[m_activeRxBuffer]);
}
if(*m_rxDma.GetIsReg() & m_rxDma.GetTeMask()) {
*m_rxDma.GetIfcReg() = m_rxDma.GetTeMask();
}
m_activeRxBuffer = !m_activeRxBuffer;
SetupReceive(m_rxBuffers[m_activeRxBuffer].buffer, bufSize);
}
template<unsigned int bufSize> void SerialConsole<bufSize>::HandleTxDmaIrq()
{
if(*m_txDma.GetIsReg() & m_txDma.GetTcMask()) { // DMA transfer complete
*m_txDma.GetIfcReg() = m_txDma.GetTcMask();
LL_USART_EnableIT_TC(m_uart);
LL_DMA_DisableStream(m_txDma.GetDma(), m_txDma.GetStream());
}
if(*m_txDma.GetIsReg() & m_txDma.GetTeMask()) {
*m_txDma.GetIfcReg() = m_txDma.GetTeMask();
m_txBuffer.error = true;
LL_USART_EnableIT_TC(m_uart);
LL_DMA_DisableStream(m_txDma.GetDma(), m_txDma.GetStream());
}
}
template<unsigned int bufSize> void SerialConsole<bufSize>::HandleUsartIrq()
{
if(LL_USART_IsActiveFlag_IDLE(m_uart) && LL_USART_IsEnabledIT_IDLE(m_uart)) { // receiver idle
// we assume that new line marker will arrive without an idle cycle even if it is CRLF
LL_USART_ClearFlag_IDLE(m_uart);
uint16_t rcvdLen = bufSize - LL_DMA_GetDataLength(m_rxDma.GetDma(), m_rxDma.GetStream());
if(rcvdLen ) {
bool newLine = false;;
do {
auto lastChar = m_rxBuffers[m_activeRxBuffer].buffer[rcvdLen-1];
if( lastChar == '\r' || lastChar == '\n')
newLine = true;
else
break;
} while(--rcvdLen);
if(newLine) {
m_rxBuffers[m_activeRxBuffer].buffer[rcvdLen] = 0;
m_rxBuffers[m_activeRxBuffer].len = rcvdLen;
LL_DMA_DisableStream(m_rxDma.GetDma(), m_rxDma.GetStream());
}
}
}
if(LL_USART_IsActiveFlag_TC(m_uart) && LL_USART_IsEnabledIT_TC(m_uart)) { // transmission complete
LL_USART_DisableIT_TC(m_uart);
LL_USART_DisableDirectionTx(m_uart); // enforcing an idle frame
LL_USART_EnableDirectionTx(m_uart);
m_txBuffer.busy = false;
if(m_callback)
m_callback->TransmissionComplete(m_callbackUserParam, &m_txBuffer);
}
}
template<unsigned int bufSize> void SerialConsole<bufSize>::Send(char const *buffer, uint8_t length)
{
if(!length) {
auto computedLength = strlen(buffer);
if(computedLength <= (uint8_t)-1)
length = computedLength;
}
if(length) {
while( m_txBuffer.busy );
memcpy(m_txBuffer.buffer, buffer, length);
SetupTransmit(m_txBuffer.buffer, length);
}
}
template<unsigned int bufSize> void SerialConsole<bufSize>::SendLine(char const *buffer, uint8_t length)
{
if(!length) {
auto computedLength = strlen(buffer);
if(computedLength <= (uint8_t)-1)
length = computedLength;
}
if(length) {
while( m_txBuffer.busy );
memcpy(m_txBuffer.buffer, buffer, length);
if(m_txBuffer.buffer[length-1 != '\n']) {
m_txBuffer.buffer[length++] = '\r';
m_txBuffer.buffer[length++] = '\n';
}
SetupTransmit(m_txBuffer.buffer, length);
}
}
#endif /* CONSOLEHANDLER_H_ */

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#include <stdint.h>
#include <f4ll_cpp/strutil.h>
//////////////////////////////////////////////////////////////////////////////
size_t strcpy_ex(char *dst, char const *src)
{
size_t ret = 0;
do {
*dst++ = *src;
++ret;
} while(*src++);
return ret - 1;
}
//////////////////////////////////////////////////////////////////////////////
void strrev(char *first, char *last)
{
char tmp;
while(last > first) {
tmp = *first;
*first++ = *last;
*last-- = tmp;
}
}
//////////////////////////////////////////////////////////////////////////////
char tochr(const uint8_t in, const uint8_t upper)
{
return in + ((in < 10) ? '0' : (upper ? 'A' : 'a') - 10);
}
//////////////////////////////////////////////////////////////////////////////
size_t uitodec(char* buffer, uint32_t data)
{
char *b2 = buffer;
if(!data) {
*b2++ = '0';
*b2 = '\0';
return 1;
}
while(data) {
*b2++ = (data % 10) + '0';
data /= 10;
}
size_t ret = b2 - buffer;
*b2-- = 0;
strrev(buffer, b2);
return ret;
}
//////////////////////////////////////////////////////////////////////////////
size_t uitohex(char* buffer, uint32_t data, uint8_t chars)
{
char *b2 = buffer;
size_t ret = 0;
if(chars == 0xff || !chars)
{
if(!data) {
*b2++ = '0';
*b2 = '\0';
return 1;
}
while(data) {
uint8_t curval = data & 0x0f;
*b2++ = tochr(curval, 1);
data >>= 4;
}
ret = b2 - buffer;
}
else
{
ret = chars;
for(uint8_t pos = 0; pos < (uint8_t)ret; ++pos) {
*b2++ = tochr(data & 0x0f, 1);
data >>= 4;
}
}
*b2-- = 0;
strrev(buffer, b2);
return ret;
}
//////////////////////////////////////////////////////////////////////////////
size_t itodec(char* buffer, int data)
{
if(data < 0) {
*buffer++ = '-';
return uitodec(buffer, -data) + 1;
}
return uitodec(buffer, data);
}
//////////////////////////////////////////////////////////////////////////////
size_t itohex(char* buffer, int data)
{
if(data < 0) {
*buffer++ = '-';
return uitohex(buffer, -data, 0) + 1;
}
return uitohex(buffer, data, 0);
}

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/*
* strutil.h
*
* Created on: Feb 11, 2017
* Author: compi
*/
#ifndef _STM32PLUS_STRUTIL_H_
#define _STM32PLUS_STRUTIL_H_
#include <stddef.h>
#include <inttypes.h>
#ifdef __cplusplus
extern "C" {
#endif
//////////////////////////////////////////////////////////////////////////////
size_t strcpy_ex(char *dst, char const *src);
size_t uitodec(char* buffer, uint32_t data);
size_t uitohex(char* buffer, uint32_t data, uint8_t chars);
size_t itodec(char* buffer, int data);
size_t itohex(char* buffer, int data);
void strrev(char *first, char *last);
char tochr(const uint8_t in, const uint8_t upper);
#ifdef __cplusplus
}
#endif
#endif /* _STM32PLUS_STRUTIL_H_ */

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/*
* UartBase.cpp
*
* Created on: Feb 4, 2020
* Author: abody
*/
#include <f4ll_cpp/uartbase.h>
UartBase::UartBase(USART_TypeDef *uart, DMA_TypeDef *dma, uint32_t stream_rx, uint32_t stream_tx)
: m_uart(uart)
, m_rxDma(dma, stream_rx)
, m_txDma(dma, stream_tx)
{
*m_rxDma.GetIfcReg() =
m_rxDma.GetTcMask() | m_rxDma.GetHtMask() |
m_rxDma.GetTeMask() | m_rxDma.GetFeMask() | m_rxDma.GetDmeMask();
*m_txDma.GetIfcReg() =
m_txDma.GetTcMask() | m_txDma.GetHtMask() |
m_txDma.GetTeMask() | m_txDma.GetFeMask() | m_txDma.GetDmeMask();
LL_DMA_EnableIT_TC(dma, stream_rx);
LL_DMA_EnableIT_TE(dma, stream_rx);
LL_DMA_EnableIT_TC(dma, stream_tx);
LL_DMA_EnableIT_TE(dma, stream_tx);
}
void UartBase::SetupReceive(void *buffer, uint16_t length)
{
LL_DMA_ConfigAddresses(m_rxDma.GetDma(), m_rxDma.GetStream(), LL_USART_DMA_GetRegAddr(m_uart),
(uint32_t)buffer, LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
LL_DMA_SetDataLength(m_rxDma.GetDma(), m_rxDma.GetStream(), length); // payload already have extra room for hash
LL_USART_EnableDMAReq_RX(m_uart);
LL_USART_ClearFlag_ORE(m_uart);
LL_DMA_EnableStream(m_rxDma.GetDma(), m_rxDma.GetStream());
}
void UartBase::SetupTransmit(void *buffer, uint16_t length)
{
LL_DMA_ConfigAddresses(m_txDma.GetDma(), m_txDma.GetStream(), (uint32_t)buffer, LL_USART_DMA_GetRegAddr(m_uart), LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
LL_DMA_SetDataLength(m_txDma.GetDma(), m_txDma.GetStream(), length);
LL_USART_EnableDMAReq_TX(m_uart);
LL_DMA_EnableStream(m_txDma.GetDma(), m_txDma.GetStream());
}

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/*
* UartBase.h
*
* Created on: Feb 4, 2020
* Author: abody
*/
#ifndef F4LL_CPP_UARTBASE_H_
#define F4LL_CPP_UARTBASE_H_
#include <platform/usart_ll.h>
#include <f4ll_cpp/dmahelper.h>
class UartBase
{
public:
UartBase() = delete;
protected:
UartBase(USART_TypeDef *uart, DMA_TypeDef *dma, uint32_t stream_rx, uint32_t stream_tx);
void SetupTransmit(void *buffer, uint16_t length);
void SetupReceive(void *buffer, uint16_t length);
USART_TypeDef *m_uart;
DmaHelper m_rxDma;
DmaHelper m_txDma;
};
#endif /* F4LL_CPP_UARTBASE_H_ */