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68 changed files with 3385 additions and 610 deletions
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@ -167,7 +167,7 @@ typedef struct
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This parameter can be a value of @ref TIM_Encoder_Mode */
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uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
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This parameter can be a value of @ref TIM_Input_Capture_Polarity */
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This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
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uint32_t IC1Selection; /*!< Specifies the input.
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This parameter can be a value of @ref TIM_Input_Capture_Selection */
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@ -179,7 +179,7 @@ typedef struct
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This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
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uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
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This parameter can be a value of @ref TIM_Input_Capture_Polarity */
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This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
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uint32_t IC2Selection; /*!< Specifies the input.
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This parameter can be a value of @ref TIM_Input_Capture_Selection */
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@ -231,7 +231,12 @@ typedef struct
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uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
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This parameter can be a value of @ref TIM_Master_Mode_Selection */
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uint32_t MasterSlaveMode; /*!< Master/slave mode selection
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This parameter can be a value of @ref TIM_Master_Slave_Mode */
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This parameter can be a value of @ref TIM_Master_Slave_Mode
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@note When the Master/slave mode is enabled, the effect of
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an event on the trigger input (TRGI) is delayed to allow a
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perfect synchronization between the current timer and its
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slaves (through TRGO). It is not mandatory in case of timer
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synchronization mode. */
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} TIM_MasterConfigTypeDef;
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/**
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@ -588,6 +593,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
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* @}
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*/
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/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
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* @{
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*/
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#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */
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#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */
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/**
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* @}
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*/
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/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
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* @{
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*/
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@ -1020,15 +1034,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
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* @retval None
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*/
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#define __HAL_TIM_DISABLE(__HANDLE__) \
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do { \
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if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
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{ \
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if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
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{ \
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(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
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} \
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} \
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} while(0)
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do { \
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if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
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{ \
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if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
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{ \
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(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
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} \
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} \
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} while(0)
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/**
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* @brief Disable the TIM main Output.
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@ -1037,15 +1051,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
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* @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
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*/
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#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
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do { \
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if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
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{ \
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if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
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{ \
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(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
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} \
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} \
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} while(0)
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do { \
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if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
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{ \
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if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
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{ \
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(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
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} \
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} \
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} while(0)
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/**
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* @brief Disable the TIM main Output.
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@ -1172,7 +1186,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
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* @arg TIM_IT_BREAK: Break interrupt
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* @retval The state of TIM_IT (SET or RESET).
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*/
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#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
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#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
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== (__INTERRUPT__)) ? SET : RESET)
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/** @brief Clear the TIM interrupt pending bits.
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* @param __HANDLE__ TIM handle
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@ -1220,8 +1235,7 @@ mode.
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* @param __HANDLE__ TIM handle.
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* @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
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*/
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#define __HAL_TIM_GET_COUNTER(__HANDLE__) \
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((__HANDLE__)->Instance->CNT)
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#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
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/**
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* @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function.
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@ -1230,18 +1244,17 @@ mode.
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* @retval None
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*/
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#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
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do{ \
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(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
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(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
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} while(0)
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do{ \
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(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
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(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
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} while(0)
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/**
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* @brief Get the TIM Autoreload Register value on runtime.
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* @param __HANDLE__ TIM handle.
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* @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
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*/
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#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
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((__HANDLE__)->Instance->ARR)
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#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
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/**
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* @brief Set the TIM Clock Division value on runtime without calling another time any Init function.
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@ -1254,11 +1267,11 @@ mode.
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* @retval None
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*/
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#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
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do{ \
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(__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \
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(__HANDLE__)->Instance->CR1 |= (__CKD__); \
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(__HANDLE__)->Init.ClockDivision = (__CKD__); \
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} while(0)
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do{ \
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(__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \
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(__HANDLE__)->Instance->CR1 |= (__CKD__); \
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(__HANDLE__)->Init.ClockDivision = (__CKD__); \
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} while(0)
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/**
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* @brief Get the TIM Clock Division value on runtime.
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@ -1268,8 +1281,7 @@ mode.
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* @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
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* @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
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*/
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#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \
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((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
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#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
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/**
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* @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
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@ -1289,10 +1301,10 @@ mode.
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* @retval None
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*/
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#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
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do{ \
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TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
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TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
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} while(0)
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do{ \
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TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
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TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
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} while(0)
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/**
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* @brief Get the TIM Input Capture prescaler on runtime.
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@ -1328,10 +1340,10 @@ mode.
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* @retval None
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*/
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#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
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(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
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((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
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((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
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((__HANDLE__)->Instance->CCR4 = (__COMPARE__)))
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(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
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((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
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((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
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((__HANDLE__)->Instance->CCR4 = (__COMPARE__)))
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/**
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* @brief Get the TIM Capture Compare Register value on runtime.
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@ -1345,10 +1357,10 @@ mode.
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* @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
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*/
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#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
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(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
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((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
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((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
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((__HANDLE__)->Instance->CCR4))
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(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
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((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
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((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
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((__HANDLE__)->Instance->CCR4))
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/**
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* @brief Set the TIM Output compare preload.
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@ -1362,10 +1374,10 @@ mode.
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* @retval None
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*/
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#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
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(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
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((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
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((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
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((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
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(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
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((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
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((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
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((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
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/**
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* @brief Reset the TIM Output compare preload.
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@ -1379,10 +1391,52 @@ mode.
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* @retval None
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*/
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#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
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(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
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((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
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((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
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((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE))
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(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
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((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
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((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
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((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE))
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/**
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* @brief Enable fast mode for a given channel.
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* @param __HANDLE__ TIM handle.
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* @param __CHANNEL__ TIM Channels to be configured.
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* This parameter can be one of the following values:
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* @arg TIM_CHANNEL_1: TIM Channel 1 selected
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* @arg TIM_CHANNEL_2: TIM Channel 2 selected
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* @arg TIM_CHANNEL_3: TIM Channel 3 selected
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* @arg TIM_CHANNEL_4: TIM Channel 4 selected
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* @note When fast mode is enabled an active edge on the trigger input acts
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* like a compare match on CCx output. Delay to sample the trigger
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* input and to activate CCx output is reduced to 3 clock cycles.
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* @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
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* @retval None
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*/
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#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
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(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
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((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
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((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
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((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE))
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/**
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* @brief Disable fast mode for a given channel.
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* @param __HANDLE__ TIM handle.
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* @param __CHANNEL__ TIM Channels to be configured.
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* This parameter can be one of the following values:
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* @arg TIM_CHANNEL_1: TIM Channel 1 selected
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* @arg TIM_CHANNEL_2: TIM Channel 2 selected
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* @arg TIM_CHANNEL_3: TIM Channel 3 selected
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* @arg TIM_CHANNEL_4: TIM Channel 4 selected
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* @note When fast mode is disabled CCx output behaves normally depending
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* on counter and CCRx values even when the trigger is ON. The minimum
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* delay to activate CCx output when an active edge occurs on the
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* trigger input is 5 clock cycles.
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* @retval None
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*/
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#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
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(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
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((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
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((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
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((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE))
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/**
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* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.
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@ -1392,8 +1446,7 @@ mode.
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* enabled)
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* @retval None
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*/
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#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
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((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
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#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
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/**
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* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
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@ -1406,8 +1459,7 @@ mode.
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* _ Update generation through the slave mode controller
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* @retval None
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*/
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#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
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((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
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#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
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/**
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* @brief Set the TIM Capture x input polarity on runtime.
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@ -1425,10 +1477,10 @@ mode.
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* @retval None
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*/
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#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
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do{ \
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TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
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TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
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}while(0)
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do{ \
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TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
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TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
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}while(0)
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/**
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* @}
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@ -1504,6 +1556,9 @@ mode.
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#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
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((__STATE__) == TIM_OCNIDLESTATE_RESET))
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#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \
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((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
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#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
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((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
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((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
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@ -1681,28 +1736,28 @@ mode.
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#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER)
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#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
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(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
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((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
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((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
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((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
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(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
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((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
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((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
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((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
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#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
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(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
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((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
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((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
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((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
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(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
|
||||
((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
|
||||
|
||||
#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
|
||||
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
|
||||
((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
|
||||
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
|
||||
((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
|
||||
|
||||
#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
|
||||
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
|
||||
((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
|
||||
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
|
||||
((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -1840,7 +1895,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel
|
|||
HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
|
||||
HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
|
||||
uint32_t *pData2, uint16_t Length);
|
||||
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -1864,17 +1920,19 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
|
|||
HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel);
|
||||
HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
|
||||
uint32_t OutputChannel, uint32_t InputChannel);
|
||||
HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,
|
||||
uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
|
||||
HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
|
||||
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
|
||||
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
|
||||
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
|
||||
uint32_t *BurstBuffer, uint32_t BurstLength);
|
||||
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
|
||||
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
|
||||
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
|
||||
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
|
||||
uint32_t *BurstBuffer, uint32_t BurstLength);
|
||||
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
|
||||
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
|
||||
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
|
||||
HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
|
||||
uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
|
|
@ -1900,7 +1958,8 @@ void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
|
|||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
|
||||
pTIM_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
||||
|
||||
|
|
@ -1930,8 +1989,8 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
|
|||
|
||||
/* Private functions----------------------------------------------------------*/
|
||||
/** @defgroup TIM_Private_Functions TIM Private Functions
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
|
||||
void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
|
||||
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
|
||||
|
|
@ -1950,8 +2009,8 @@ void TIM_ResetCallback(TIM_HandleTypeDef *htim);
|
|||
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
* @}
|
||||
*/
|
||||
/* End of private functions --------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue