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68 changed files with 3385 additions and 610 deletions
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@ -13576,7 +13576,7 @@ typedef struct
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#define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
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#define ETH_DMASR_TPS_Suspended_Pos (21U)
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#define ETH_DMASR_TPS_Suspended_Msk (0x3UL << ETH_DMASR_TPS_Suspended_Pos) /*!< 0x00600000 */
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#define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailabe */
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#define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailable */
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#define ETH_DMASR_TPS_Closing_Pos (20U)
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#define ETH_DMASR_TPS_Closing_Msk (0x7UL << ETH_DMASR_TPS_Closing_Pos) /*!< 0x00700000 */
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#define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
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@ -13598,7 +13598,7 @@ typedef struct
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#define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
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#define ETH_DMASR_RPS_Queuing_Pos (17U)
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#define ETH_DMASR_RPS_Queuing_Msk (0x7UL << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */
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#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */
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#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */
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#define ETH_DMASR_NIS_Pos (16U)
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#define ETH_DMASR_NIS_Msk (0x1UL << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */
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#define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
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@ -15295,10 +15295,6 @@ typedef struct
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((INSTANCE) == TIM8) || \
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((INSTANCE) == TIM9) || \
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((INSTANCE) == TIM12))
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/****************** TIM Instances : supporting synchronization ****************/
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#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
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/********************** TIM Instances : 32 bit Counter ************************/
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#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
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((INSTANCE) == TIM5))
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@ -122,11 +122,11 @@
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#endif /* USE_HAL_DRIVER */
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/**
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* @brief CMSIS version number V2.6.3
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* @brief CMSIS version number V2.6.4
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*/
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#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
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#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
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#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */
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#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x04U) /*!< [15:8] sub2 version */
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#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
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#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
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|(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
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