Clan up the structure
This commit is contained in:
parent
340f0329fa
commit
45141798d8
42 changed files with 134 additions and 452 deletions
10
components/app/CMakeLists.txt
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10
components/app/CMakeLists.txt
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add_library(app STATIC
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src/app.cpp
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src/irq_bridge.cpp
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)
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target_include_directories(app PUBLIC
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${CMAKE_CURRENT_SOURCE_DIR}/inc
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)
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target_link_libraries(app PUBLIC stm32cubemx platform f1ll)
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11
components/app/inc/app.h
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11
components/app/inc/app.h
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#pragma once
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#if defined(__cplusplus)
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extern "C" {
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#endif
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void app_main();
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#if defined(__cplusplus)
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}
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#endif
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16
components/app/inc/irq_bridge.h
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16
components/app/inc/irq_bridge.h
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#ifndef IRQ_BRIDGE_H_
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#define IRQ_BRIDGE_H_
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#if defined(__cplusplus)
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extern "C" {
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#endif
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void usart1_tx_dma_isr();
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void usart1_rx_dma_isr();
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void usart1_isr();
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#if defined(__cplusplus)
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}
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#endif
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#endif // IRQ_BRIDGE_H_
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16
components/app/src/app.cpp
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16
components/app/src/app.cpp
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#include <app.h>
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#include <main.h>
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#include <f1ll/console_handler.h>
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void app_main()
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{
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f1ll::console_handler::init(USART1, DMA1, LL_DMA_CHANNEL_5, LL_DMA_CHANNEL_4);
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while (true) {
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f1ll::console_handler::instance().print("->> Hello <<-\r\n");
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LL_GPIO_TogglePin(LED_GPIO_Port, LED_Pin);
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LL_mDelay(500);
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}
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}
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18
components/app/src/irq_bridge.cpp
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18
components/app/src/irq_bridge.cpp
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#include <irq_bridge.h>
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#include <f1ll/console_handler.h>
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void usart1_tx_dma_isr() // DMA1 channel 4
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{
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f1ll::console_handler::instance().tx_dma_isr();
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}
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void usart1_rx_dma_isr() // DMA1 channel 5
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{
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f1ll::console_handler::instance().rx_dma_isr();
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}
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void usart1_isr()
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{
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f1ll::console_handler::instance().usart_isr();
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}
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15
components/f1ll/CMakeLists.txt
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15
components/f1ll/CMakeLists.txt
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@ -0,0 +1,15 @@
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add_library(f1ll STATIC
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src/usart_core.cpp
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src/dma_helper.cpp
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src/str_util.cpp
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src/console_handler.cpp
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)
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target_include_directories(f1ll PUBLIC
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${CMAKE_CURRENT_SOURCE_DIR}/inc
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)
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target_link_libraries(f1ll PUBLIC platform stm32cubemx)
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# ST code quality workaround - Suppres register storage class warning (C++17...)
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target_compile_options(f1ll PRIVATE -Wno-register)
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47
components/f1ll/inc/f1ll/console_handler.h
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47
components/f1ll/inc/f1ll/console_handler.h
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/*
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* ll_consolehandler.h
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*
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* Created on: Nov 7, 2019
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* Author: abody
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*/
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#ifndef LL_CONSOLEHANDLER_H_
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#define LL_CONSOLEHANDLER_H_
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#include "f1ll/usart_core.h"
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#include "singleton.h"
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namespace f1ll {
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class console_handler : public usart_core, public singleton<console_handler>
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{
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friend class singleton<console_handler>;
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public:
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void print(char const *s);
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void flush();
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void append(char const *s);
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private:
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console_handler(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t channelRx, uint32_t channelTx);
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// LL_UsartCore pure virtual function implementations
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virtual void receiver_idle(void) override;
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virtual void transmission_complete(void) override;
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virtual void framing_error(void) override;
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virtual void overrun(void) override;
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virtual void rx_dma_transfer_complete(void) override;
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virtual void rx_dma_half_transfer(void) override;
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virtual void rx_dma_error(void) override;
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virtual void tx_dma_transfer_complete(void) override;
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virtual void tx_dma_half_transfer(void) override;
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virtual void tx_dma_error(void) override;
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char m_buffer[128];
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uint16_t m_used = 0;
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volatile bool m_busy = false;
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};
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} // namespace f1ll
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#endif /* LL_CONSOLEHANDLER_H_ */
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49
components/f1ll/inc/f1ll/dma_helper.h
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49
components/f1ll/inc/f1ll/dma_helper.h
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/*
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* ll_dmahelper.h
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*
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* Created on: Oct 25, 2019
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* Author: abody
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*/
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#ifndef LL_DMAHELPER_H_
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#define LL_DMAHELPER_H_
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#include <inttypes.h>
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#include <platform/dma_ll.h>
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namespace f1ll {
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class dma_helper
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{
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public:
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dma_helper(DMA_TypeDef *dma, uint32_t channel);
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dma_helper(dma_helper const &base) = default;
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inline DMA_TypeDef *get_dma() const { return m_dma; }
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inline uint32_t get_channel() const { return m_channel; }
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inline volatile uint32_t *get_is_reg() const { return m_is_reg; }
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inline volatile uint32_t *get_ifc_reg() const { return m_ifc_reg; }
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inline uint32_t get_te_mask() const { return m_te_masks[m_channel - 1]; }
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inline uint32_t get_ht_mask() const { return m_ht_masks[m_channel - 1]; }
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inline uint32_t get_tc_mask() const { return m_tc_masks[m_channel - 1]; }
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inline uint32_t get_gi_mask() const { return m_gi_masks[m_channel - 1]; }
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inline bool is_enabled_it_te() { return LL_DMA_IsEnabledIT_TE(m_dma, m_channel) != 0; }
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inline bool is_enabled_it_ht() { return LL_DMA_IsEnabledIT_HT(m_dma, m_channel) != 0; }
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inline bool is_enabled_it_tc() { return LL_DMA_IsEnabledIT_TC(m_dma, m_channel) != 0; }
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private:
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DMA_TypeDef *m_dma;
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uint32_t m_channel;
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volatile uint32_t *m_is_reg;
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volatile uint32_t *m_ifc_reg;
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static const uint32_t m_te_masks[7];
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static const uint32_t m_ht_masks[7];
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static const uint32_t m_tc_masks[7];
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static const uint32_t m_gi_masks[7];
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};
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} /* namespace f4ll */
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#endif /* LL_DMAHELPER_H_ */
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30
components/f1ll/inc/f1ll/singleton.h
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30
components/f1ll/inc/f1ll/singleton.h
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#ifndef SINGLETON_H_
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#define SINGLETON_H_
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#include <utility>
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namespace f1ll {
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template <typename T> class singleton
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{
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public:
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static T &instance() { return *m_instance; }
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template <typename... args_t> static T &init(args_t &&...args)
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{
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static T instance{std::forward<args_t>(args)...};
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m_instance = &instance;
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return instance;
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}
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protected:
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singleton() = default;
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singleton(const singleton &) = delete;
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singleton &operator=(const singleton &) = delete;
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static T *m_instance;
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};
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template <typename T> T *singleton<T>::m_instance = nullptr;
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} // namespace f1ll {
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#endif /* SINGLETON_H_ */
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31
components/f1ll/inc/f1ll/str_util.h
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31
components/f1ll/inc/f1ll/str_util.h
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/*
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* strutil.h
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*
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* Created on: Feb 11, 2017
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* Author: compi
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*/
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#ifndef _STM32PLUS_STRUTIL_H_
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#define _STM32PLUS_STRUTIL_H_
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#include <stddef.h>
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#include <inttypes.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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//////////////////////////////////////////////////////////////////////////////
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size_t strcpy_ex(char *dst, char const *src);
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size_t uitodec(char* buffer, uint32_t data);
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size_t uitohex(char* buffer, uint32_t data, uint8_t chars);
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size_t itodec(char* buffer, int data);
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size_t itohex(char* buffer, int data);
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void strrev(char *first, char *last);
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char tochr(const uint8_t in, const uint8_t upper);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _STM32PLUS_STRUTIL_H_ */
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55
components/f1ll/inc/f1ll/usart_core.h
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55
components/f1ll/inc/f1ll/usart_core.h
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/*
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* ll_dmadrivenusartcore.h
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*
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* Created on: Nov 4, 2019
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* Author: abody
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*/
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#ifndef LL_USARTCORE_H_
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#define LL_USARTCORE_H_
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#include <platform/usart_ll.h>
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#include "f1ll/dma_helper.h"
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namespace f1ll {
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class usart_core
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{
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public:
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static inline void usart_irq(usart_core *_this) { _this->usart_isr(); }
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static inline void rx_dma_irq(usart_core *_this) { _this->rx_dma_isr(); }
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static inline void tx_dma_irq(usart_core *_this) { _this->tx_dma_isr(); }
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void setup_transmit(void const *buffer, uint16_t length);
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void setup_receive(void *buffer, uint16_t length);
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protected:
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usart_core(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t channel_rx, uint32_t stream_tx);
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USART_TypeDef *m_usart;
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dma_helper m_rxDma;
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dma_helper m_txDma;
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private:
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virtual void receiver_idle(void) = 0;
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virtual void transmission_complete(void) = 0;
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virtual void framing_error(void) = 0;
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virtual void overrun(void) = 0;
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virtual void rx_dma_transfer_complete(void) = 0;
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virtual void rx_dma_half_transfer(void) = 0;
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virtual void rx_dma_error(void) = 0;
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virtual void tx_dma_transfer_complete(void) = 0;
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virtual void tx_dma_half_transfer(void) = 0;
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virtual void tx_dma_error(void) = 0;
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public:
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void usart_isr();
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void rx_dma_isr();
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void tx_dma_isr();
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};
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} // namespace f1ll
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#endif /* LL_USARTCORE_H_ */
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65
components/f1ll/src/console_handler.cpp
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65
components/f1ll/src/console_handler.cpp
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/*
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* ll_consolehandler.cpp
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*
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* Created on: Nov 7, 2019
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* Author: abody
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*/
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#include <f1ll/console_handler.h>
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#include <string.h>
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namespace f1ll {
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console_handler::console_handler(USART_TypeDef *usart, DMA_TypeDef *dma, uint32_t channelRx, uint32_t channelTx)
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: usart_core(usart, dma, channelRx, channelTx)
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{
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}
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void console_handler::receiver_idle(void) {}
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void console_handler::transmission_complete(void)
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{
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m_busy = false;
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m_used = 0;
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}
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void console_handler::framing_error(void) {}
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void console_handler::overrun(void) {}
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void console_handler::rx_dma_transfer_complete(void) {}
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void console_handler::rx_dma_half_transfer(void) {}
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void console_handler::rx_dma_error(void) {}
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void console_handler::tx_dma_transfer_complete(void)
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{
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LL_USART_EnableIT_TC(m_usart);
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LL_DMA_DisableChannel(m_txDma.get_dma(), m_txDma.get_channel());
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}
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void console_handler::tx_dma_half_transfer(void) {}
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void console_handler::tx_dma_error(void) {}
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void console_handler::append(char const *s)
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{
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while (m_busy)
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;
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size_t len = strlen(s);
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size_t max_len = sizeof(m_buffer) - m_used;
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strncpy(m_buffer + m_used, s, max_len);
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m_used += len < max_len ? len : max_len;
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}
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void console_handler::flush()
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{
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while (m_busy)
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;
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if (m_used) {
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m_busy = true;
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setup_transmit(m_buffer, m_used);
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}
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}
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void console_handler::print(char const *s)
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{
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append(s);
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flush();
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}
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} // namespace f1ll
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38
components/f1ll/src/dma_helper.cpp
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38
components/f1ll/src/dma_helper.cpp
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/*
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q * ll_dmahelper.cpp
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*
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* Created on: Oct 25, 2019
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* Author: abody
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*/
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#include <f1ll/dma_helper.h>
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namespace f1ll {
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const uint32_t dma_helper::m_te_masks[7] = {
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DMA_ISR_TEIF1, DMA_ISR_TEIF2, DMA_ISR_TEIF3, DMA_ISR_TEIF4,
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DMA_ISR_TEIF5, DMA_ISR_TEIF6, DMA_ISR_TEIF7};
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const uint32_t dma_helper::m_ht_masks[7] = {
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DMA_ISR_HTIF1, DMA_ISR_HTIF2, DMA_ISR_HTIF3, DMA_ISR_HTIF4,
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DMA_ISR_HTIF5, DMA_ISR_HTIF6, DMA_ISR_HTIF7};
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const uint32_t dma_helper::m_tc_masks[7] = {
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DMA_ISR_TCIF1, DMA_ISR_TCIF2, DMA_ISR_TCIF3, DMA_ISR_TCIF4,
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DMA_ISR_TCIF5, DMA_ISR_TCIF6, DMA_ISR_TCIF7};
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const uint32_t dma_helper::m_gi_masks[7] = {
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DMA_ISR_GIF1, DMA_ISR_GIF2, DMA_ISR_GIF3, DMA_ISR_GIF4,
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DMA_ISR_GIF5, DMA_ISR_GIF6, DMA_ISR_GIF7};
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dma_helper::dma_helper(DMA_TypeDef *dma, uint32_t channel)
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: m_dma(dma), m_channel(channel)
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#ifdef DMA2
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,
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m_is_reg(dma == DMA1 ? &DMA1->ISR : &DMA2->ISR),
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m_ifc_reg(dma == DMA1 ? &DMA1->IFCR : &DMA2->IFCR)
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#else
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,
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m_is_reg(&DMA1->ISR), m_ifc_reg(&DMA1->IFCR)
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#endif
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{
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}
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} // namespace f1ll
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98
components/f1ll/src/str_util.cpp
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98
components/f1ll/src/str_util.cpp
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#include <f1ll/str_util.h>
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#include <stdint.h>
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|
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//////////////////////////////////////////////////////////////////////////////
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size_t strcpy_ex(char *dst, char const *src) {
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size_t ret = 0;
|
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do {
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*dst++ = *src;
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++ret;
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} while (*src++);
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return ret - 1;
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}
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|
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//////////////////////////////////////////////////////////////////////////////
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void strrev(char *first, char *last) {
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char tmp;
|
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while (last > first) {
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tmp = *first;
|
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*first++ = *last;
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*last-- = tmp;
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}
|
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}
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|
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//////////////////////////////////////////////////////////////////////////////
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char tochr(const uint8_t in, const uint8_t upper) {
|
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return in + ((in < 10) ? '0' : (upper ? 'A' : 'a') - 10);
|
||||
}
|
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|
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//////////////////////////////////////////////////////////////////////////////
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size_t uitodec(char *buffer, uint32_t data) {
|
||||
char *b2 = buffer;
|
||||
if (!data) {
|
||||
*b2++ = '0';
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*b2 = '\0';
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return 1;
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}
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|
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while (data) {
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*b2++ = (data % 10) + '0';
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data /= 10;
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}
|
||||
size_t ret = b2 - buffer;
|
||||
|
||||
*b2-- = 0;
|
||||
|
||||
strrev(buffer, b2);
|
||||
return ret;
|
||||
}
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
size_t uitohex(char *buffer, uint32_t data, uint8_t chars) {
|
||||
char *b2 = buffer;
|
||||
size_t ret = 0;
|
||||
|
||||
if (chars == 0xff || !chars) {
|
||||
if (!data) {
|
||||
*b2++ = '0';
|
||||
*b2 = '\0';
|
||||
return 1;
|
||||
}
|
||||
|
||||
while (data) {
|
||||
uint8_t curval = data & 0x0f;
|
||||
*b2++ = tochr(curval, 1);
|
||||
data >>= 4;
|
||||
}
|
||||
ret = b2 - buffer;
|
||||
|
||||
} else {
|
||||
ret = chars;
|
||||
for (uint8_t pos = 0; pos < (uint8_t)ret; ++pos) {
|
||||
*b2++ = tochr(data & 0x0f, 1);
|
||||
data >>= 4;
|
||||
}
|
||||
}
|
||||
*b2-- = 0;
|
||||
strrev(buffer, b2);
|
||||
return ret;
|
||||
}
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
size_t itodec(char *buffer, int data) {
|
||||
if (data < 0) {
|
||||
*buffer++ = '-';
|
||||
return uitodec(buffer, -data) + 1;
|
||||
}
|
||||
|
||||
return uitodec(buffer, data);
|
||||
}
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
size_t itohex(char *buffer, int data) {
|
||||
if (data < 0) {
|
||||
*buffer++ = '-';
|
||||
return uitohex(buffer, -data, 0) + 1;
|
||||
}
|
||||
return uitohex(buffer, data, 0);
|
||||
}
|
119
components/f1ll/src/usart_core.cpp
Normal file
119
components/f1ll/src/usart_core.cpp
Normal file
|
@ -0,0 +1,119 @@
|
|||
/*
|
||||
* ll_dmadrivenusartcore.cpp
|
||||
*
|
||||
* Created on: Nov 4, 2019
|
||||
* Author: abody
|
||||
*/
|
||||
|
||||
#include <f1ll/usart_core.h>
|
||||
|
||||
namespace f1ll {
|
||||
|
||||
usart_core::usart_core(USART_TypeDef *usart, DMA_TypeDef *dma,
|
||||
uint32_t channelRx, uint32_t channelTx)
|
||||
: m_usart(usart), m_rxDma(dma, channelRx), m_txDma(dma, channelTx) {
|
||||
uint32_t status = usart->SR;
|
||||
volatile uint32_t tmpreg =
|
||||
usart->DR; // clearing some of the error/status bits in the USART
|
||||
(void)tmpreg;
|
||||
(void)status;
|
||||
|
||||
*m_txDma.get_ifc_reg() = m_txDma.get_gi_mask();
|
||||
*m_rxDma.get_ifc_reg() = m_rxDma.get_gi_mask();
|
||||
|
||||
LL_DMA_EnableIT_HT(dma, channelRx);
|
||||
LL_DMA_EnableIT_TC(dma, channelRx);
|
||||
LL_DMA_EnableIT_TE(dma, channelRx);
|
||||
LL_DMA_EnableIT_HT(dma, channelTx);
|
||||
LL_DMA_EnableIT_TC(dma, channelTx);
|
||||
LL_DMA_EnableIT_TE(dma, channelTx);
|
||||
}
|
||||
|
||||
void usart_core::usart_isr() {
|
||||
uint32_t status = m_usart->SR;
|
||||
volatile uint32_t tmpreg =
|
||||
m_usart->DR; // clearing some of the error/status bits in the HW
|
||||
(void)tmpreg;
|
||||
|
||||
if (LL_USART_IsEnabledIT_TC(m_usart) &&
|
||||
LL_USART_IsActiveFlag_TC(m_usart)) { // transmission complete
|
||||
LL_USART_DisableIT_TC(m_usart);
|
||||
transmission_complete();
|
||||
}
|
||||
if (LL_USART_IsEnabledIT_IDLE(m_usart) && (status & USART_SR_IDLE)) {
|
||||
receiver_idle();
|
||||
}
|
||||
if (LL_USART_IsEnabledIT_ERROR(m_usart)) {
|
||||
if (status & USART_SR_FE) {
|
||||
framing_error();
|
||||
}
|
||||
if (status & USART_SR_ORE) {
|
||||
overrun();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void usart_core::rx_dma_isr() {
|
||||
if (*m_rxDma.get_is_reg() & m_rxDma.get_tc_mask()) {
|
||||
*m_rxDma.get_ifc_reg() = m_rxDma.get_tc_mask();
|
||||
if (m_rxDma.is_enabled_it_tc()) {
|
||||
rx_dma_transfer_complete();
|
||||
}
|
||||
}
|
||||
if (*m_rxDma.get_is_reg() & m_rxDma.get_ht_mask()) {
|
||||
*m_rxDma.get_ifc_reg() = m_rxDma.get_ht_mask();
|
||||
if (m_rxDma.is_enabled_it_ht()) {
|
||||
rx_dma_half_transfer();
|
||||
}
|
||||
}
|
||||
if (*m_rxDma.get_is_reg() & m_rxDma.get_te_mask()) {
|
||||
*m_rxDma.get_ifc_reg() = m_rxDma.get_te_mask();
|
||||
if (m_rxDma.is_enabled_it_te()) {
|
||||
rx_dma_error();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void usart_core::tx_dma_isr() {
|
||||
if (*m_txDma.get_is_reg() & m_txDma.get_tc_mask()) { // DMA transfer complete
|
||||
*m_txDma.get_ifc_reg() = m_txDma.get_tc_mask();
|
||||
if (m_txDma.is_enabled_it_tc()) {
|
||||
tx_dma_transfer_complete();
|
||||
}
|
||||
}
|
||||
if (*m_txDma.get_is_reg() & m_txDma.get_ht_mask()) {
|
||||
*m_txDma.get_ifc_reg() = m_txDma.get_ht_mask();
|
||||
if (m_txDma.is_enabled_it_ht()) {
|
||||
tx_dma_half_transfer();
|
||||
}
|
||||
}
|
||||
if (*m_txDma.get_is_reg() & m_txDma.get_te_mask()) {
|
||||
*m_txDma.get_ifc_reg() = m_txDma.get_te_mask();
|
||||
if (m_txDma.is_enabled_it_te()) {
|
||||
tx_dma_error();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void usart_core::setup_transmit(void const *buffer, uint16_t length) {
|
||||
LL_DMA_ConfigAddresses(m_txDma.get_dma(), m_txDma.get_channel(),
|
||||
reinterpret_cast<uint32_t>(buffer),
|
||||
LL_USART_DMA_GetRegAddr(m_usart),
|
||||
LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
|
||||
LL_DMA_SetDataLength(m_txDma.get_dma(), m_txDma.get_channel(), length);
|
||||
LL_USART_EnableDMAReq_TX(m_usart);
|
||||
LL_DMA_EnableChannel(m_txDma.get_dma(), m_txDma.get_channel());
|
||||
}
|
||||
|
||||
void usart_core::setup_receive(void *buffer, uint16_t length) {
|
||||
LL_DMA_ConfigAddresses(m_rxDma.get_dma(), m_rxDma.get_channel(),
|
||||
LL_USART_DMA_GetRegAddr(m_usart),
|
||||
reinterpret_cast<uint32_t>(buffer),
|
||||
LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
|
||||
LL_DMA_SetDataLength(m_rxDma.get_dma(), m_rxDma.get_channel(), length);
|
||||
LL_USART_EnableDMAReq_RX(m_usart);
|
||||
LL_USART_ClearFlag_ORE(m_usart);
|
||||
LL_DMA_EnableChannel(m_rxDma.get_dma(), m_rxDma.get_channel());
|
||||
}
|
||||
|
||||
} // namespace f1ll
|
13
components/platform/CMakeLists.txt
Normal file
13
components/platform/CMakeLists.txt
Normal file
|
@ -0,0 +1,13 @@
|
|||
cmake_minimum_required(VERSION 3.22)
|
||||
|
||||
add_library(platform INTERFACE)
|
||||
|
||||
# Enable CMake support for ASM and C languages
|
||||
enable_language(C CXX ASM)
|
||||
|
||||
target_include_directories(platform INTERFACE ${CMAKE_CURRENT_SOURCE_DIR})
|
||||
|
||||
target_link_libraries(platform INTERFACE)
|
||||
|
||||
|
||||
|
6
components/platform/platform/crc_ll.h
Normal file
6
components/platform/platform/crc_ll.h
Normal file
|
@ -0,0 +1,6 @@
|
|||
#ifndef __PLATFORM_CRC_LL_H_INCLUDED
|
||||
#define __PLATFORM_CRC_LL_H_INCLUDED
|
||||
|
||||
#include "crc.h"
|
||||
|
||||
#endif // __PLATFORM_CRC_LL_H_INCLUDED
|
6
components/platform/platform/dma_ll.h
Normal file
6
components/platform/platform/dma_ll.h
Normal file
|
@ -0,0 +1,6 @@
|
|||
#ifndef __PLATFORM_DMA_LL_H_INCLUDED
|
||||
#define __PLATFORM_DMA_LL_H_INCLUDED
|
||||
|
||||
#include "stm32f1xx_ll_dma.h"
|
||||
|
||||
#endif // __PLATFORM_DMA_LL_H_INCLUDED
|
6
components/platform/platform/gpio_ll.h
Normal file
6
components/platform/platform/gpio_ll.h
Normal file
|
@ -0,0 +1,6 @@
|
|||
#ifndef __PLATFORM_USART_LL_H_INCLUDED
|
||||
#define __PLATFORM_USART_LL_H_INCLUDED
|
||||
|
||||
#include <stm32f1xx_ll_gpio.h>
|
||||
|
||||
#endif // __PLATFORM_USART_LL_H_INCLUDED
|
6
components/platform/platform/usart_ll.h
Normal file
6
components/platform/platform/usart_ll.h
Normal file
|
@ -0,0 +1,6 @@
|
|||
#ifndef __PLATFORM_USART_LL_H_INCLUDED
|
||||
#define __PLATFORM_USART_LL_H_INCLUDED
|
||||
|
||||
#include <stm32f1xx_ll_usart.h>
|
||||
|
||||
#endif // __PLATFORM_USART_LL_H_INCLUDED
|
6
components/platform/platform/utils_ll.h
Normal file
6
components/platform/platform/utils_ll.h
Normal file
|
@ -0,0 +1,6 @@
|
|||
#ifndef __PLATFORM_USART_LL_H_INCLUDED
|
||||
#define __PLATFORM_USART_LL_H_INCLUDED
|
||||
|
||||
#include <stm32f1xx_ll_utils.h>
|
||||
|
||||
#endif // __PLATFORM_USART_LL_H_INCLUDED
|
Loading…
Add table
Add a link
Reference in a new issue